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19-4456; Rev 0; 2/09
KIT ATION EVALU E AILABL AV
Dual RF LDMOS Bias Controllers with I2C/SPI Interface
General Description
The MAX1385/MAX1386 set and control bias conditions for dual RF LDMOS power devices found in cellular base stations. Each device includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor LDMOS drain current over the 20mA to 5A range. Two external diode-connected transistors monitor LDMOS temperatures while an internal temperature sensor measures the local die temperature of the MAX1385/MAX1386. A 12-bit ADC converts the programmable-gain amplifier (PGA) outputs, external/internal temperature readings, and two auxiliary inputs. The two gate-drive channels, each consisting of 8-bit coarse and 10-bit fine DACs and a gate-drive amplifier, generate a positive gate voltage to bias the LDMOS devices. The MAX1385 includes a gate-drive amplifier with a gain of 2 and the MAX1386 gate-drive amplifier provides a gain of 4. The 8-bit coarse and 10-bit fine DACs allow up to 18 bits of resolution. The MAX1385/ MAX1386 include autocalibration features to minimize error over time, temperature, and supply voltage. The MAX1385/MAX1386 feature an I2C/SPITM-compatible serial interface. Both devices operate from a 4.75V to 5.25V analog supply (3.2mA supply current), a 2.7V to 5.25V digital supply (3.1mA supply current), and a 4.75V to 11.0V gate-drive supply (4.5mA supply current). The MAX1385/MAX1386 are available in a 48-pin thin QFN package.
Features
Integrated High-Side Drain Current-Sense PGA with Gain of 2, 10, or 25 0.5% Accuracy for Sense Voltage Between 75mV and 250mV Full-Scale Sense Voltage of 100mV with Gain of 25 Full-Scale Sense Voltage of 250mV with Gain of 10 Common-Mode Range of 5V to 30V Drain Voltage for LDMOS Adjustable Low Noise 0 to 5V, 0 to 10V Output Gate-Bias Voltage Ranges with 10mA Gate Drive Fast Clamp to 0V for LDMOS Protection 8-Bit DAC Control of Gate-Bias Voltage 10-Bit DAC Control of Gate-Bias Offset with Temperature Internal Die Temperature Measurement External Temperature Measurement by DiodeConnected Transistor (2N3904) Internal 12-Bit ADC Measurement of Temperature, Current, and Voltages Selectable I2C-/SPI-Compatible Serial Interface 400kHz/1.7MHz/3.4MHz I2C-Compatible Control for Settings and Data Measurement 16MHz SPI-Compatible Control for Settings and Data Measurement Internal 2.5V Reference Three Address Inputs to Control Eight Devices in I2C Mode
MAX1385/MAX1386
Applications
RF LDMOS Bias Control in Cellular Base Stations Industrial Process Control
Ordering Information/Selector Guide
PART MAX1385AETM+** MAX1385BETM+ MAX1386AETM+** MAX1386BETM+** TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 48 Thin QFN-EP* 48 Thin QFN-EP* 48 Thin QFN-EP* 48 Thin QFN-EP* TEMP ERROR (C) 1 2 1 2 VGATE (V) 5 5 10 10
*EP = Exposed pad. **Future product--contact factory for availability. +Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration and Typical Operating Circuit (I2C Mode) appear at end of data sheet. SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CS1+, CS1-, CS2+, CS2- to GATEGND.................-0.3V to +32V CS1- to CS1+, CS2- to CS2+ ...................................-6V to +0.3V GATEVDD to GATEGND .........................................-0.3V to +12V GATE1, GATE2 to GATEGND ...........-0.3V to (GATEVDD + 0.3V) SAFE1, SAFE2 to GATEGND....................................-0.3V to +6V GATEGND to AGND..............................................-0.3V to +0.3V All Other Analog Inputs to AGND ............-0.3V to the lower of +6V and (AVDD + 0.3V) Digital Inputs to DGND ............-0.3V to the lower of +6V and (DVDD + 0.3V) SDA/DIN, SCL to DGND...........................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Maximum Continuous Current into Any Pin ........................50mA Continuous Power Dissipation (TA = +70C) 48-Pin, 7mm x 7mm, Thin QFN (derate 27.8 mW/C above +70C).............................................................2222mW Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Common-Mode Input Voltage Range Common-Mode Rejection Ratio Input-Bias Current SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE CURRENT SENSE WITH PGA VCS+, VCSCMRR ICS+ ICSFull-Scale Sense Voltage Range VSENSE = VCS_+ VCS_PGA gain = 25 PGA gain = 10 PGA gain = 2 PGA gain = 25 Sense Voltage Range for Accuracy of 0.5% VSENSE Sense Voltage Range for Accuracy of 2% VSENSE Total PGAOUT Voltage Error PGAOUT Capacitive Load PGAOUT Settling Time Saturation Recovery Time CPGAOUT tHSCS Settles to within 0.5% of final value, RS = 50, CGATE = 15pF Settles to within 0.5% accuracy; from VSENSE = 3 x full scale AvPGA = 2 Sense-Amplifier Slew Rate AvPGA = 10 AvPGA = 25 < 25 < 45 0.5 2 2 V/s PGA gain = 10 PGA gain = 2 PGA gain = 25 PGA gain = 10 PGA gain = 2 VSENSE = 75mV 0 0 0 75 75 75 20 20 20 0.1 11V < VCS+ < 30V VSENSE < 100mV over the common-mode range 5 90 120 0.002 195 2 100 250 1250 100 250 1250 100 250 1250 0.5 100 % pF s s mV mV mV 30 V dB A
2
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Sense-Amplifier Bandwidth LDMOS GATE DRIVER (GAIN = 2 and 4) IGATE = 1mA Output Gate-Drive Voltage Range VGATE IGATE = 10mA Output Impedance VGATE Settling Time Output Capacitive Load (Note 1) VGATE Noise Maximum Power-On Transient Output Short-Circuit Current Limit Total Unadjusted Error No Autocalibration and Offset Removal (Note 2) Total Adjusted Error With Autocalibration and Offset Removal Drift Clamp to Zero Delay Output Safe Switch OnResistance Amplifier Bandwidth Amplifier Slew Rate MONITOR ADC DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Offset Temperature Coefficient (Note 5) NADC DNLADC INLADC (Note 4) 12 0.5 0.6 2 2 0.4 0.4 2 2 4 4 Bits LSB LSB LSB LSB ppm/C ppm/C ROPSW GATE_ clamped to AGND (Note 3) MAX1385 MAX1386 300 150 0.375 ISC TUE MAX1386, LOCODE = 128, HICODE = 180 MAX1385, LOCODE = 128, HICODE = 180 TUE MAX1386, LOCODE = 128, HICODE = 180 MAX1385, VGATE > 1V MAX1386, VGATE > 1V 2 15 30 1 500 16 V/C s kHz V/s 12 1 40 8 mV 1s, sinking or sourcing MAX1385, LOCODE = 128, HICODE = 180 RGATE tGATE CGATE Measured at DC Settles to within 0.5% of final value; RSERIES = 50, CGATE = 15F No series resistance, RSERIES = 0 RSERIES = 50 RMS noise; 1kHz - 1MHz 0 0 250 100 25 6 20 mV 1 0.1 10 10 25,000 0.75 GATEVDD - 0.75 V GATEVDD -1 ms nF nV/Hz mV mA SYMBOL AvPGA = 2 AvPGA = 10 AvPGA = 25 CONDITIONS MIN TYP 900 720 290 kHz MAX UNITS
MAX1385/MAX1386
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3
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching MONITOR ADC DYNAMIC ACCURACY (1kHz sine-wave input, 2.5VP-P, up to 94.4ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth MONITOR ADC CONVERSION RATE Power-Up Time Conversion Time Input Range Input Leakage Current Input Capacitance TEMPERATURE MEASUREMENTS MAX1385A/MAX1386A, TA = +25C Internal Sensor Measurement Error (Note 1) MAX1385A/MAX1386A, TA = TMIN to TMAX MAX1385B/MAX1386B, TA = +25C MAX1385B/MAX1386B, TA = TMIN to TMAX External Sensor Measurement Error (Notes 1, 7) Temperature Resolution External Diode Drive Drive Current Ratio INTERNAL REFERENCE REFADC/REFDAC Output Voltage REFADC/REFDAC Output Temperature Coefficient REFADC/REFDAC Output Impedance VREFADC VREFDAC TCREFADC, TCREFDAC TA = +25C TA = +25C 2.494 2.494 2.500 2.500 14 6.5 2.506 2.506 V ppm/C k (Note 8) 2.8 16.5 TA = +25C TA = TMIN to TMAX -3 -2.0 -1.0 0.25 0.25 0.25 0.35 0.4 0.75 1/8 85 +3 +2.0 C C/LSB A +1.0 C CADCIN tPU tCONV VADCIN External reference Internal reference Internally clocked Relative to AGND (Note 6) VIN = 0V and VIN = AVDD 0 0.01 34 0.8 70 7.5 10 VREF 1 s s V A pF SINAD THD SFDR IMD fIN1 = 0.99kHz, fIN2 = 1.02kHz -3dB point S/(N + D) > 68dB Up to the 5th harmonic 70 -82 86 76 10 100 dB dB dB dB MHz kHz SYMBOL CONDITIONS MIN TYP 0.1 0.1 MAX UNITS LSB LSB
MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)
4
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Capacitive Bypass at REF Power-Supply Rejection Ratio EXTERNAL REFERENCE REFADC Input Voltage Range REFADC Input Current REFDAC Input Voltage Range REFDAC Input Current Resolution Integral Nonlinearity Differential Nonlinearity Resolution Integral Nonlinearity Differential Nonlinearity POWER SUPPLIES (Note 10) Analog Supply Voltage Digital Supply Voltage Gate-Drive Supply Voltage Analog Supply Current Digital Supply Current GATEVDD Supply Current Shutdown Current (Note 11) AVDD DVDD VGATEVDD IAVDD IDVDD IGATEVDD IAVDD IPD IDVDD IVDDGATE AVDD = 5V DVDD = 2.7V to 5.25V 3 4.75 2.7 4.75 3.2 3.1 4.5 0.1 0.1 0.1 5.25 AVDD + 0.3 11.00 4 4.3 7 2 2 2 A V V V mA mA mA NCDAC INLCDAC Measured at GATE; fine DAC set at full scale DNLCDAC Guaranteed monotonic NFDAC INLFDAC Measured at GATE; coarse DAC set at full scale 10 0.25 0.1 4 1 VREFADC IREFADC VREFDAC Limited code test VREF = 2.5V, fSAMPLE = 174ksps Acquisition/between conversions (Note 9) Static current when no DAC calibration 8 0.15 0.05 1 0.5 0.5 0.1 1.0 60 0.01 AVDD 80 1 2.5 V A V A Bits LSB LSB Bits LSB LSB PSRR AVDD = +5V 5% SYMBOL CONDITIONS MIN 270 70 TYP MAX UNITS nF dB
MAX1385/MAX1386
GATE-DRIVER COARSE-DAC DC ACCURACY
GATE-DRIVER FINE-DAC DC ACCURACY
DNLFDAC Guaranteed monotonic
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5
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x DVDD 0.3 x DVDD 0.1 x DVDD 2.4 0.4 2.2 0.7 ISINK = 3mA ISOURCE = 2mA DVDD - 0.5 0.4 DVDD - 0.5 0.4 TYP MAX UNITS
VIH AND VIL FOR SDA/DIN AND SCL IN I2C OPERATION ONLY Input High Voltage Input Low Voltage Input Hysteresis VIH VIL VHYS V V V
VIH AND VIL FOR OPSAFE1 AND OPSAFE2 Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output Low Voltage Output High Voltage VIH VIL VIH VIL VOL VOH V V V V V V
VIH AND VIL FOR ALL OTHER DIGITAL INPUTS
VOH AND VOL FOR A1/DOUT (SPI), SDA/DIN, ALARM
VOH AND VOL FOR SAFE1, SAFE2, BUSY Output Low Voltage Output High Voltage VOL VOH ISINK = 0.5mA ISOURCE = 0.5mA V V
6
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
I2C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 12, see Figure 1)
(GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = -40C to +85C, unless otherwise noted).
PARAMETER Serial-Clock Frequency Bus Free Time Between STOP and START Condition Hold Time Repeated START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time Repeated START Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Signal, Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spikes Suppressed by the Input Filter SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tF tSU;STO Cb tSP (Note 16) 0 (Note 14) (Note 14) (Notes 14, 15) (Note 13) After this period, the first clock pulse is generated CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 0 0 20 + 0.1Cb 0.6 400 50 300 300 250 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns s pF ns
MAX1385/MAX1386
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7
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
I2C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2)
(GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = -40C to +85C, unless otherwise noted).
PARAMETER Serial-Clock Frequency Setup Time Repeated START Condition Hold Time Repeated START Condition SCL Pulse-Width Low SCL Pulse-Width High Data Setup Time Data Hold Time Rise Time of SCL Signal, Receiving Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit, Receiving Fall Time of SCL Signal, Receiving Rise Time of SDA Signal, Receiving Fall Time of SDA Signal, Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spikes That are Suppressed by the Input Filter SYMBOL fSCL tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tRCL (Note 17) CONDITIONS MIN 0 160 160 160 60 10 0 10 70 40 TYP MAX 3.4 UNITS MHz ns ns ns ns ns ns ns
tRCL1
10
80
ns
tFCL tRDA tFDA tSU;STO Cb tSP (Note 18)
10 10 10 160
40 80 80
ns ns ns ns
100 0 10
pF ns
8
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
SPI TIMING CHARACTERISTICS (Note 12, See Figure 3)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = -40C to +85C, unless otherwise noted.)
PARAMETER SCL Clock Period SCL High Time SCL Low Time DIN Setup Time DIN Hold Time SCL Fall to DOUT Transition CSB Fall to DOUT Enable CSB Rise to DOUT Disable CSB Rise or Fall to SCL Rise CSB Pulse-Width High Last Clock Rise to CSB Rise SYMBOL tCP tCH tCL tDS tDH tDO tDV tTR tCSS tCSW tCSH CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF (Note 12) 25 100 50 CONDITIONS MIN 62.5 25 25 10 0 20 40 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
MAX1385/MAX1386
Note 1: Guaranteed by design. Note 2: Total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit DACs and the gate driver. They are all measured at the GATE1 and GATE2 outputs. Offset removal refers to presetting the drain current after a room temperature calibration by the user. This effectively removes the channel offset. Note 3: During power-on reset, the output safe switch is closed. The output safe switch opens once both AVDD and DVDD supply voltages are established. Note 4: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors have been removed. Note 5: Offset nulled. Note 6: Absolute range for analog inputs is from 0 to AVDD. Note 7: The MAX1385/MAX1386 and external sensor are at the same temperature. External sensor measurement error is tested with a diode-connected 2N3904. Note 8: The drive current ratio is defined as the large drive current divided by the small drive current in a temperature measurement. See the Temperature Measurements section for further details. Note 9: Guaranteed monotonicity. Accuracy might be degraded at lower VREFDAC. Note 10: Supply current limits are valid only when digital inputs are at DVDD or DGND. Timing specifications are only guaranteed when inputs are driven rail-to-rail. Note 11: Shutdown supply currents are typically 0.1A. Maximum specification is limited by automated test equipment. Note 12: All timing specifications referred to VIH or VIL levels. Note 13: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of SCL) to bridge the undefined region of SCL's falling edge. Note 14: Cb = total capacitance of one bus line in pF; tR and tF are measured between 0.3 x DVDD and 0.7 x DVDD. Note 15: For a device operating in an I2C-compatible system. Note 16: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 17: A device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. An input circuit with a threshold as low as possible for the falling edge of the SCL signal minimizes this hold time. Note 18: Cb = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be linearly interpolated.
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9
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
SDA tF tLOW t SU;DAT
tR
tF
t HD;STA
tSP
tr
tBUF
SCL t HD;STA S t SU;STA Sr t SU;STO P S
t HD;DAT
t HIGH
Figure 1. I2C Slow-/Fast-Mode Timing Diagram
Sr t FDA SDA t SU;STA t HD;DAT t SU;DAT SCL t RCL1 t HIGH t FCL t LOW t RCL t LOW t HIGH t SU;STO t RDA Sr P
t HD;STA
t RCL1
Figure 2. I2C High-Speed-Mode Timing Diagram
tCSW CSB tCSS SCL tDH DIN D23 tDV DOUT D1 tDS D22 D1 tDO D0 D0 tTR tCL tCH tCP tCSH tCSS
Figure 3. SPI Timing Diagram
10
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Typical Operating Characteristics
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = +25C, unless otherwise noted.)
AVDD SUPPLY CURRENT vs. AVDD VOLTAGE
MAX1385/86 toc01
MAX1385/MAX1386
DVDD SUPPLY CURRENT vs. DVDD VOLTAGE
4.00 3.75 3.50 3.25 3.00 IDVDD (mA) 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00
MAX1385/86 toc02
GATEVDD SUPPLY CURRENT vs. GATEVDD VOLTAGE
4.9 4.8 4.7 IGATEVDD (mA) 4.6 4.5 4.4 4.3 4.2 4.1 4.0 TA = -40C TA = +25C AvPGA = 2 CMV = 12V VSENSE = 100mV
MAX1385/86 toc03
4.0 3.9 3.8 3.7 IAVDD (mA) 3.6 3.5 3.4 3.3 3.2 3.1 3.0 4.7 4.8 4.9 5.0 AVDD (V) 5.1 5.2 TA = -40C TA = +85C TA = +25C AvPGA = 2 CMV = 12V VSENSE = 100mV
5.0
AvPGA = 2 CMV = 12V VSENSE = 100mV
TA = +85C TA = +25C TA = -40C
TA = +85C
5.3
2.7
3.2
3.7
4.2 DVDD (V)
4.7
5.2
4
5
6
7
8
9
10
11
12
GATEVDD (V)
TOTAL PGAOUT_ ERROR vs. TEMPERATURE
MAX1385/86 toc04
TOTAL PGAOUT_ ERROR vs. VSENSE
MAX1385/86 toc05
TOTAL PGAOUT_ ERROR vs. VSENSE
0 -0.5 PGAOUT_ ERROR (%) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 AvPGA = 25 CMV = 12V
MAX1385/86 toc06
0.150 0.125 0.100 0.075 0.050 0.025 0 -0.025 -0.050 -0.075 -0.100 -0.125 -0.150
AvPGA = 2 CMV = 12V VSENSE = 100mV ACQUISITION TRACKING
0.50 0.45 0.40 PGAOUT_ ERROR (%) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
0.5
AvPGA = 2 CMV = 12V
PGAOUT_ ERROR (%)
-40 -25 -10
5
20
35
50
65
80
0
250
500
750
1000
1250
0
20
40
60
80
100
TEMPERATURE (C)
VSENSE (mV)
VSENSE (mV)
TOTAL PGAOUT_ ERROR vs. COMMON-MODE VOLTAGE
MAX1385/86 toc07
PGAOUT_ OFFSET VOLTAGE vs. TEMPERATURE
200 150 100 50 0 -50 -100 -150 -200 -250 -300 -350 -400 TRACKING AvPGA = 2 CMV = 12V VSENSE = 100mV ACQUISITION
MAX1385/86 toc08
VSENSE TRANSIENT RESPONSE
0.10 0.09 0.08 PGAOUT_ ERROR (%) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 5 10 15 20 25 30 COMMON-MODE VOLTAGE (V) AvPGA = 2 VSENSE = 100mV
MAX1385/86 toc09
OFFSET VOLTAGE (V)
100mV/div VSENSE PGAOUT_ 1V/div
-40 -25 -10
5
20
35
50
65
80
10s/div
TEMPERATURE (C)
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = +25C, unless otherwise noted.)
PGAOUT_ 0mV TO 250mV VSENSE TRANSIENT RESPONSE PGAOUT_ PEDESTAL ERROR DURING CALIBRATION
MAX1385/86 toc11
MAX1385/86 toc10
GATE_ OFFSET COMPENSATED ERROR vs. TEMPERATURE
-1
MAX1385/86 toc12
0
100mV/div VSENSE
ERROR VOLTAGE (mV)
2V/div BUSY
-2 -3 -4 -5 -6 -7 -8
H_ERROR, AUTOCALIBRATION
PGAOUT_ 1V/div PGAOUT_ 10mV/div 10s/div 20s/div
L_ERROR, AUTOCALIBRATION H_ERROR, NO AUTOCALIBRATION
L_ERROR, NO AUTOCALIBRATION
-40 -25 -10
5
20
35
50
65
80
TEMPERATURE (C)
VGATE vs. POWER-ON TIME
GATE_ SETTLING TIME vs. LOAD CAPACITANCE
RSERIES = 50 14 50mV/div SETTLING TIME (ms) 12 10 8 6 4 2 0
MAX1385/86 toc14
MAX1385/86 toc13
CHARGE CURRENT vs. VGATE
16
MAX1385/86 toc15
VGATE_ 2V/div
VGATE_
20mA/div IGATE_
400s/div
0.1
1
10
100
1ms/div
LOAD CAPACITANCE (F)
GATE_ VOLTAGE SWING vs. LOAD RESISTANCE
9 GATE_ VOLTAGE SWING (V) 8 7 6 5 4 3 2 1 0 10 100 1000 10,000 100,000
MAX1385/86 toc16
GLITCH ENERGY
MAX1385/86 toc17
10
10mV/div
1s/div
LOAD RESISTANCE ()
12
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT COARSE DAC)
MAX1385/86 toc18
MAX1385/MAX1386
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT FINE DAC)
MAX1385/86 toc19
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT DAC)
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1385/86 toc20
1.0 0.8 0.6 0.4 INL (LSB)
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 50 100 150 200 250 DIGITAL INPUT CODE
0
200
400
600
800
1000
0
50
100
150
200
250
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT FINE DAC)
MAX1385/86 toc21
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (ADC)
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1385/86 toc22
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 400 600 800 1000 DIGITAL INPUT CODE
1.0
0
1000
2000
3000
4000
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (ADC)
MAX1385/86 toc23
FFT PLOT
-20 -40 AMPLITUDE (dB) -60 -80 -100 -120 -140 -160 fIN = 303Hz fSAMPLE = 49.15kHz
MAX1385/86 toc24
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1000 2000 3000
0
4000
0
5
10
15
20
25
DIGITAL OUTPUT CODE
FREQUENCY (kHz)
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13
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1F, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE vs. TEMPERATURE
MAX1385/86 toc25
ADC OFFSET ERROR vs. TEMPERATURE
AVDD = 5V 0.075 0.050 OFFSET ERROR (%) 0.025 0 -0.025 -0.050
MAX1385/86 toc26
2.509 2.504 2.499 2.494
0.100
AVDD = 5V
REFERENCE VOLTAGE (V)
2.489 -0.075 2.484 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) -0.100 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
ADC OFFSET ERROR vs. AVDD VOLTAGE
MAX1385/86 toc27
ADC GAIN ERROR vs. TEMPERATURE
0.04 0.03 GAIN ERROR (%) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 AVDD = 5V
MAX1385/86 toc28 MAX1385/86 toc30
0.100 0.075 0.050 OFFSET ERROR (%) 0.025 0
0.05
-0.025 -0.050 -0.075 -0.100 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V)
-40 -25 -10
5
20
35
50
65
80
TEMPERATURE (C)
INTERNAL TEMPERATURE SENSOR ERROR vs. TEMPERATURE
MAX1385/86 toc29
EXTERNAL TEMPERATURE SENSOR ERROR vs. TEMPERATURE
1.0 0.8 0.6 0.4 ERROR (C) 0.2 0 -0.2 -0.4 -0.6
0 -0.2 -0.4 ERROR (C) -0.6 -0.8 -1.0 -1.2 -1.4 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-0.8 -1.0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
14
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Pin Description
PIN 1 2 3 4 5 6 NAME DGND SAFE1 A0/CSB CNVST SEL ALARM Digital Ground Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when programmed channel 1 temperature threshold or current threshold has been reached. I2C-Compatible Address 0/ SPI-Compatible Chip Select. See the Digital Serial Interface section. In SPI mode, drive A0/CSB low to select the device. Active-Low Conversion-Start Input. Drive CNVST low to start a conversion (clock modes 01 and 11). Connect CNVST to DVDD when initiating conversions through the serial interface (clock mode 00). Mode Select. Connect SEL to DGND to select I2C mode. Connect SEL to DVDD to select SPI mode. Alarm Output. Program ALARM for comparator or interrupt output modes (see the Alarm Modes section). Program ALARM to assert on any combination of channel temperature or current thresholds. Safe Status Channel 2 Output. Programmable active-high or active-low. SAFE2 asserts when programmed channel 2 temperature threshold or current threshold has been reached. No Connection. Not internally connected. DAC Reference Input/Output ADC Reference Input/Output Diode Positive Input 1. Connect to anode of temperature diode or the base and collector of an npn transistor. Diode Negative Input 1. Connect to cathode of temperature diode or the emitter of an npn transistor. Diode Positive Input 2. Connect to anode of temperature diode or the base and collector of an npn transistor. Diode Negative Input 2. Connect to cathode of temperature diode or the emitter of an npn transistor. ADC Input 1 ADC Input 2 Programmable-Gain Amplifier Output 2 Analog Power-Supply Input Analog Ground FUNCTION
MAX1385/MAX1386
7 8, 19, 25, 28, 35-39, 42, 46 9 10 11 12 13 14 15 16 17 18 20, 21, 22
SAFE2 N.C. REFDAC REFADC DXP1 DXN1 DXP2 DXN2 ADCIN1 ADCIN2 PGAOUT2 AVDD AGND
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Pin Description (continued)
PIN 23 24 26 27 29 30 31 32 33 34 40 41 43 44 45 47 48 -- NAME GATEGND GATEVDD OPSAFE2 CS2+ CS2GATE2 GATE1 CS1CS1+ OPSAFE1 PGAOUT1 A2/N.C. SCL SDA/DIN A1/DOUT BUSY DVDD EP Gate-Drive Amplifier Ground Gate-Drive Amplifier Supply Input Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND. Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2 supply. Current-Sense Negative Input 2. CS2- is the external sense resistor connection to the LDMOS 2 drain. Channel 2 Gate-Drive Amplifier Output Channel 1 Gate-Drive Amplifier Output Current-Sense Negative Input 1. CS1- is the external sense resistor connection to the LDMOS 1 drain. Current-Sense Positive Input 1. CS1+ is the external sense resistor connection to the LDMOS 1 supply. Operating Safe Channel 1 Input. Drive OPSAFE1 high to clamp GATE1 to AGND. Programmable-Gain Amplifier Output 1 I2C-Compatible Address 2. See the Digital Serial Interface section. No Connection. Leave unconnected in SPI mode. Digital Serial Clock Input I2C-Compatible Serial Data Input/Output SPI-Compatible Serial Data Input I2C-Compatible Address 1. See the Digital Serial Interface section. SPI-Compatible Serial Data Output Device Busy Output. See the BUSY Output section Digital Supply Input Exposed Pad. Connect to AGND. Internally connected to analog ground. FUNCTION
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Functional Diagram
SAFE2 SAFE1 ALARM AVDD
MAX1385/MAX1386
DVDD DGND
DIGITAL CURRENT AND TEMPERATURE COMPARATORS PGA1
PGAOUT1 CS1+ CS1-
PGA REGISTERS CS2SCL SDA/DIN A0/CSB A1/DOUT A2/N.C. CHANNEL 1 DAC REGISTERS 8-BIT HIGH CODE 8-BIT LOW CODE 10-BIT FINE ADJUST CODE 10-BIT DAC DRV GATE1 GATEVDD GATEGND CHANNEL 1 DAC REGISTERS 8-BIT HIGH CODE 8-BIT LOW CODE 10-BIT FINE ADJUST CODE 10-BIT DAC AGND DRV GATE2 VREFDAC OPSAFE2 VREFDAC OPSAFE1 SERIAL INTERFACE REGISTER SECTION PGA2 CS2+ PGAOUT2
MAX1385 MAX1386
TEMP SENSOR PGAOUT1 PGAOUT2 MUX EXTERNAL TEMP PROCESSING ADCIN0 ADCIN1 DXP1 DXN1 DXP2 DXN2
FIFO MEMORY
12-BIT ADC WITH T/H
VREFDAC
2.5V REF
VREFADC
CONVERSION AND SCAN OSCILLATOR AND CONTROL
REFDAC REFADC
CNVST
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17
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Detailed Description
The MAX1385/MAX1386 set and control bias conditions for dual RF LDMOS power devices found in cellular base stations. Each device includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor the LDMOS drain current over the 20mA to 5A range. Two external diode-connected transistors monitor the LDMOS temperatures while an internal temperature sensor measures the local die temperature of the MAX1385/MAX1386. A 12-bit ADC converts the programmable-gain amplifier (PGA) outputs, external/internal temperature readings, and two auxiliary inputs. The two gate-drive channels, each consisting of 8-bit coarse and 10-bit fine DACs and a gate-drive amplifier, generate a positive gate voltage to bias the LDMOS devices. The MAX1385 includes a gate-drive amplifier with a gain of 2 and the MAX1386 gate-drive amplifier provides a gain of 4. The 8-bit coarse and 10-bit fine DACs allow up to 18 bits of resolution. The MAX1385/ MAX1386 include autocalibration modes to minimize error over time, temperature, and supply voltage. The MAX1385/MAX1386 feature an I2C-/SPI-compatible serial interface. Both devices operate from a 4.75V to 5.25V analog supply (3.2mA supply current), a 2.7V to 5.25V digital supply (3.1mA supply current), and a 4.75V to 11.0V gate-drive supply (4.5mA supply current). The internal ADC block converts the results of the die temperature, remote diode temperature readings, PGAOUT1, PGAOUT2, ADCIN1, or ADCIN2 voltages according to which bits are set in the ADC Conversion register (see the ADCCON (Write) section). The results of the conversions are written to FIFO memory. The FIFO holds up to 15 words (each word is 16 bits) with channel tags to indicate which channel the 12-bit data comes from. The FIFO indicates an overflow condition and an underflow condition (read of an empty FIFO) by the Flag register (see the RDFLAG (Read) section) and channel tags. The FIFO always stores the most recent conversion results and allows the oldest data to be overwritten. Read the latest result stored in the FIFO by sending the appropriate read command byte (see the FIFO (Read) section). Read the data stored in the FIFO through the FIFO Read register. The FIFO (Read) section details which channel is being read and whether the FIFO has overflowed.
Analog-to-Digital Conversion Scheduling
The MAX1385/MAX1386 ADC multiplexer scans selected inputs in the order shown in Table 1. The ADC multiplexer skips over the items that are not selected in the Analog-to-Digital Conversion register. When writing a conversion command before a conversion is complete, the pending conversion may be canceled. In addition, using the serial interface while the ADC is converting may degrade the performance of the ADC.
Power-On Reset
On power-up, the MAX1385/MAX1386 are in full powerdown mode (see the SSHUT (Write) section). To change to normal power mode, write two commands to the Software Shutdown register. The first command sets FULLPD to 0 (other bits in the Software Shutdown register are ignored). A second command is needed to activate any internal blocks. The recommended sequence of commands to ensure reliable startup following the application of power, is given in the Appendix: Recommended Power-Up Code Sequence section.
ADC Clock Modes The MAX1385/MAX1386 offer three different conversion/acquisition modes (known as clock modes) selectable through the Device Configuration register (see the DCFIG (Read/Write) section). Clock Mode 10 is reserved and cannot be used. For conversion/acquisition examples and timing diagrams, see the Applications Information section.
If the analog-to-digital conversion requires the internal reference (temperature measurement or voltage measurement with internal reference selected) and the reference has not been previously forced on, the device inserts a worst-case delay of 81s, for the reference to settle, before commencing the analog-to-digital conversion. The reference remains powered up while there are pending conversions. If the reference is not forced on, it automatically powers down at the end of a scan or when CONCONV in the Analog-to-Digital Conversion register is set back to 0.
ADC Description
The MAX1385/MAX1386 ADC uses a fully differential successive approximation register (SAR) conversion technique and on-chip track-and-hold (T/H) circuitry to convert temperature and voltage signals into 12-bit digital results. The analog inputs accept single-ended input signals. Single-ended signals are converted using a unipolar transfer function. See the ADC transfer function of Figure 25 for more information.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Clock Mode 00 In clock mode 00, power-up, acquisition, conversion, and power-down are all initiated by writing to the Analogto-Digital Conversion register and performed automatically using the internal oscillator. This is the default clock mode. The ADC sets the BUSY output high, powers up, scans all requested channels, stores the results in the FIFO, and then powers down. After the scan is complete, BUSY is pulled low and the results for all the commanded channels are available in the FIFO. Clock Mode 01 In clock mode 01, power-up, acquisition, conversion, and power-down are all initiated by setting CNVST low for at least 40ns. Conversions are performed automatically using the internal oscillator. The ADC sets the BUSY output high, powers up, scans all requested channels, stores the results in the FIFO, and then powers down. After the scan is complete, BUSY is pulled low and the results for all the commanded channels are available in the FIFO. Clock Mode 11 In clock mode 11, conversions are initiated one at a time through CNVST in the order shown in Table 1 and performed using the internal oscillator. In this mode, the acquisition time is controlled by the time CNVST is brought low. CNVST is resynchronized by the internal oscillator, which means there is a one-clock-cycle uncertainty (typically 320ns) in the exact sampling instant. Different timing parameters apply depending whether the conversion is temperature, voltage, using the external reference, or using the internal reference.
For a temperature conversion, set CNVST low for at least 40ns. The BUSY output goes high and the temperature conversion results are available after an additional 94s (when BUSY goes low again). Thus, the worst-case conversion time of the initial temperature sensor scan (allowing the internal reference to settle) is 175s. Subsequent temperature scans only take 85s worst case as the internal reference and temperature sensor circuits are already powered. For a voltage conversion while using an internal or external reference, set CNVST low for at least 2s but less than 6.7s. The BUSY output goes high and the conversion results are available after an additional 7.5s (typ) when BUSY goes low again. Continuous conversion is not supported in this clock mode (see the ADCCON (Write) section).
MAX1385/MAX1386
Changing Clock Modes During ADC Conversions If a change is made to the clock mode in the Device Configuration register while the ADC is already performing a conversion (or series of conversions), the following descriptions show how the MAX1385/MAX1386 respond: * CKSEL = 00 and is then changed to another value
The ADC completes the already triggered series of conversions and then goes idle. The BUSY output remains high until the conversions are completed. The MAX1385/MAX1386 then respond in accordance with the new CKSEL mode. * CKSEL = 01 and is then changed to another value If waiting for the initial external trigger, the MAX1385/MAX1386 immediately exit clock mode 01, power down the ADC, and go idle. The BUSY output stays low and waits for the external trigger. If a conversion sequence has started, the ADC completes the requested conversions and then goes idle. The BUSY output remains high until the conversions are completed. The MAX1385/MAX1386 then respond in accordance with the new CKSEL mode. * CKSEL = 11 and is then changed to another value If waiting for an external trigger, the MAX1385/ MAX1386 immediately exit clock mode 11, power down the ADC, and go idle. The BUSY output stays low and waits for the external trigger.
Table 1. Order of ADC Conversion Scan
ORDER OF SCAN 1 2 3 4 5 6 7 DESCRIPTION OF CONVERSION Internal device temperature External diode 1 temperature PGAOUT1 for current sense ADCIN1 External diode 2 temperature PGAOUT2 for current sense ADCIN2
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19
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
CAPACITIVE DAC
ADCIN_
CONTROL LOGIC
AGND
TRACK MODE CAPACITIVE DAC
ADCIN_
CONTROL LOGIC
AGND
HOLD/CONVERSION MODE
Figure 4. Equivalent ADC Input Circuit
Analog Input Track and Hold The equivalent circuit (Figure 4) shows the MAX1385/MAX1386 ADC input architecture. In track mode, a positive input capacitor is connected to ADCIN_ and a negative input capacitor is connected to AGND. After the T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted. The input capacitance charging rate determines the time required for the T/H to acquire an input signal. If the input signal's source impedance is high, the required acquisition time lengthens.
Any source impedance below 300 does not significantly affect the ADC's AC performance. A high-imped-
ance source can be accommodated either by lengthening tACQ or by placing a 1F capacitor between the positive input and AGND. The combination of the analog input source impedance and the capacitance at the analog input creates an RC filter that limits the analoginput bandwidth.
Analog-Input Bandwidth The ADC's input-tracking circuitry has a 10MHz bandwidth to digitize high-speed transient events. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Analog-Input Protection Internal ESD protection diodes clamp all analog inputs to AVDD and AGND, allowing the inputs to swing from AGND - 0.3V to AVDD + 0.3V without damage. If an analog input voltage exceeds the supplies, limit the input current to 2mA.
commands. The output of a coarse DAC is not updated until the appropriate DAC output register(s) have been set. See Figure 5 for the relationship between DAC input registers, DAC output registers, and wipers. DAC output registers are not directly accessible to the user. Choose which input register to write to based on whether automatic low or high calibration is desired, or if updates to the output of the DAC need to be initiated immediately. In the case of automatic low or high calibration, a correction code is added to or subtracted from the 10-bit fine-DAC input register. Transfers from the DAC input registers to DAC output registers can occur immediately after a write to the appropriate DAC input register or on a software command through the Software LDAC register. See the Register Descriptions section for bit-level descriptions of these registers.
MAX1385/MAX1386
DAC Description
The MAX1385/MAX1386 include two 8-bit and 10-bit DAC blocks to independently control the voltage on each LDMOS gate. Both 10-bit and 8-bit DACs can be automatically calibrated to minimize output error over time, temperature, and supply voltage. The 8-bit and 10-bit DACs have unipolar transfer functions and have a relationship to the output voltage by the following equation:
V V FINECODE VDACOUT = REF x LOCODE + REF x [HICODE - LOCODE] x 28 28 210
where LOCODE, HICODE, and FINECODE are the low wiper (8 bits), high wiper (8 bits), and fine DAC (10 bits) values written to the DAC by the user. LOCODE, HICODE, and FINECODE represent the values in the DAC input registers and may or may not be the actual values in the DAC output registers depending whether autocalibration is used or not (see the 8-Bit CoarseDAC Adjustment section). To find the actual voltage at GATE_, multiply the VDACOUT result by 2 (MAX1385) or 4 (MAX1386). Due to the buffer amplifiers, the voltage at GATE_ cannot be set below 100mV above AGND. It is recommended that the LOCODE for DAC1 and DAC2 are set so that the minimum possible output at GATE_ is 200mV (MAX1385) and 400mV (MAX1386). The DACs can be operated to produce an 18-bit monotonic DAC with 12-bit (typ) INL. Write to either HICODE or LOCODE in a leapfrog fashion, without commanding autocalibration, to configure the 18-bit monotonic DAC. When LOCODE > HICODE, invert the value of FINECODE.
8-Bit Coarse-DAC Adjustment Each DAC control block contains a resistor string with wipers that serve as an 8-bit coarse DAC. Wipers are set by writing to the appropriate DAC input registers and/or using the Load DAC Control register (LDAC)
10-Bit Fine-DAC Adjustment Each DAC control block contains a 10-bit fine DAC that operates between the high and low wiper positions from the 8-bit coarse DAC. The 10-bit fine DAC also has an optional automatic calibration mode and can be updated immediately or on a software-issued command in the Software LDAC register. Writing to the appropriate fine-DAC input register determines whether automatic calibration is used and/or when the DAC is updated. See Figure 6 for the relationship between DAC input registers, DAC output registers, and the Software LDAC register. The fine-DAC output registers are not directly accessible. Choose which DAC input register to write to based on whether automatic fine calibration is desired, or whether updates to the output of the DAC need to be initiated immediately. In the case of automatic fine calibration, a correction code is added to or subtracted from the input register code and transferred to the appropriate fine-DAC output register. Transfers from a fine-DAC input register to a fine-DAC output register can occur immediately after a write to the appropriate DAC input register or on a software command through the Software LDAC register. See the Register Descriptions section for bit-level detail of these registers.
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21
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
HIGH-CAL
COARSE DAC_ HIGH WIPER OUTPUT REGISTER HIWIPE_ REGISTER HCAL
INPUT REGISTERS
THRUHI_ REGISTER
VDACREF TO 10-BIT FINE DAC
THRULO_ REGISTER
LOWIPE_ REGISTER
LCAL
COARSE DAC_ LOW WIPER OUTPUT REGISTER
LOW-CAL
LOAD DAC CONTROL REGISTER (LDAC)
Figure 5. Coarse-DAC Register Diagram
FROM 8-BIT COARSE DAC
LOAD DAC CONTROL REGISTER (LDAC)
FINE_ REGISTER
INPUT REGISTERS
FINECAL_ REGISTER FINE DAC_ OUTPUT REGISTER
10-BIT FINE DAC
TO GATE-DRIVE BLOCK
FINECALTHRU_ REGISTER
FINE-CAL
FINETHRU_ REGISTER
FROM 8-BIT COARSE DAC
Figure 6. Fine-DAC Register Diagram
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
ADC/DAC References
The MAX1385/MAX1386 provide an internal low-noise 2.5V reference for the ADCs, DACs, and temperature sensor. See the Device Configuration Register section for information on configuring the device for external or internal reference. Connect a voltage source to REFADC in the 1V to AVDD range when using an external ADC reference. Connect a voltage source to REFDAC in the 0.5V to 2.5V range when using an external DAC reference. When using an external voltage reference, bypass the reference pin with a 0.1F capacitor to AGND. The internal reference has a lowpass filter to reduce noise. The device allows 60s (typ) and 81s (typ) worst case for the reference to settle before permitting an analog-to-digital conversion. If reference mode 11 is selected, the required settling time is longer. In this case, the user should set at least one of DAC1PD, DAC2PD, or FBGON in the Software Shutdown register, any of which forces the reference to be permanently powered up. The external temperature-sensor drive current ratio has been optimized for a 2N3904 npn transistor with an ideality factor of 1.0065. The nonideality offset is removed internally by a preset digital coefficient. Use of a transistor with a different ideality factor produces a proportionate difference in the absolute measured temperature. More details on this topic and others related to using an external temperature sensor can be found in Maxim Application Note 1057: Compensating for Ideality and Series Resistance Differences Between Thermal Sense Diodes and Application Note 1944: Temperature Monitoring Using the MAX1253/MAX1254 and MAX1153/MAX1154.
MAX1385/MAX1386
High-Side Current-Sense PGAs
The MAX1385/MAX1386 provide two high-side currentsense amplifiers with programmable gain. The currentsense amplifiers are unidirectional and provide a 5V to 30V input common-mode range. Both CS1+ and CS2+ must be within the specified common-mode range for proper operation of each amplifier. The sense amplifiers measure the load current, ILOAD, through an external sense resistor, RSENSE_, between the CS_+ and CS_- inputs. The full-scale sense voltage range (VSENSE_ = VCS_+ - VCS_-) depends on the programmed gain, AvPGA_ (see the DCFIG (Read/Write) section). The sense amplifiers provide a voltage output at PGAOUT_ according to the following equation: VPGAOUT _ = AvPGA _ x (VCS _ + - VCS _ -) These outputs are also routed to the internal 12-bit ADC so that a digital representation of the amplified voltages can be read through the FIFO. The PGA scales the sensed voltages to fit the input range of the ADC. Program the PGA with gains of 2, 10, and 25 by setting the PGSET_ bits (see the DCFIG (Read/Write) section). The input stages have nominal input offset voltages of 0mV that can be adjusted by a trim DAC (not shown in the Functional Diagram) over the -3mV to +3mV range in 25V steps. Autocalibration can be used to control the trim DAC to minimize the effective channel input offset voltage (see the PGACAL (Write) section). The PGA feedback network is referenced to AGND.
Temperature Measurements
The MAX1385/MAX1386 measure the internal die temperature and two external remote-diode temperature sensors. Set up a temperature conversion by writing to the Analog-to-Digital Conversion register (see the ADCCON (Write) section). Optionally program SAFE1 and SAFE2 outputs to depend on programmed temperature thresholds. The MAX1385/MAX1386 can perform temperature measurements with an internal diode-connected transistor. The diode bias current changes from 66A to 4A to produce a temperature-dependent bias voltage difference. The second conversion result at 4A is subtracted from the first at 66A to calculate a digital value that is proportional to the absolute temperature. The stored data result is the aforementioned digital code minus an offset to adjust from Kelvin to Celsius. The reference voltage for the temperature measurements is always derived from the internal reference source. Temperature results are in degrees Celsius (two's-complement form). The temperature-sensing circuits power up for the first temperature measurement in an analog-to-digital conversion scan. The temperature-sensing circuits remain powered until the end of the scan to avoid a possible 67s delay of internal reference power-up time for each individual temperature channel. If the continuous convert bit CONCONV is set high and the current ADC channel selection includes a temperature channel, the temperature-sensor circuits remain powered up until the CONCONV bit is set low.
ALARM Output
The state of ALARM is logically equivalent to the inclusive OR of SAFE1 and SAFE2. The exception to this statement is when ALARM is configured for output interrupt mode (see the Alarm Modes section). When in output-interrupt mode, ALARM stays in its asserted state until its associated flag is cleared by reading from the
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
HIGHEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR HIGH THRESHOLD REGISTER) ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL BUILT-IN 8 TO 64 LSBs OF HYSTERESIS RANGE OF VALUES THAT DO NOT CAUSE AN ALARM BUILT-IN 8 TO 64 LSBs OF HYSTERESIS ALARM OUTPUT ASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL ALARM OUTPUT DEASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL* HIGH THRESHOLD
LOW THRESHOLD ALARM OUTPUT DEASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL* LOWEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR HIGH THRESHOLD REGISTER)
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE. WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ FOR ALARM TO BE DEASSERTED.
Figure 7. Window-Threshold-Mode Diagram
Flag register. Configure ALARM for open-drain/pushpull and active-high/active-low by setting the respective bits in the Hardware Alarm Configuration register.
BUSY Output
The BUSY output is forced high to show that the MAX1385/MAX1386 are busy for a variety of reasons: * The ADC is in the middle of a user-commanded conversion cycle (but not in continuous convert mode) * The ADC is in the middle of an internally triggered conversion cycle (for a self-calibration measurement) * The device is in the middle of DAC calibration calculations * The device is in the middle of power-up initialization * One of the PGA channels is undergoing self-calibration The serial interface remains active regardless of the state of the BUSY output. Wait until BUSY goes low to read the current conversion data from the FIFO. When BUSY is high as a result of an ADC conversion, do not enter a second conversion command until BUSY has gone low to indicate the previous conversion is complete. The rising edge of BUSY occurs on the next internal oscillator clock after the start of a new conversion (either by CNVST or an interface command).
SAFE1/SAFE2 Outputs
Set up the SAFE1 and SAFE2 outputs to allow WiredOR/AND-type logic functions or to create additional interrupt-type signals to replace or supplement the existing ALARM output. SAFE1 and SAFE2 do not have any internal pullup/pulldown devices. The SAFE1 and SAFE2 output buffers are CMOS-compatible, noninverting, output buffers capable of driving to within 0.5V of either digital rail. The SAFE1 and SAFE2 outputs power up as active-high CMOS outputs with standard logic levels. Configure the SAFE1 and SAFE2 outputs for open-drain or push-pull by setting the appropriate bits in the Hardware Alarm Configuration register. When configuring SAFE1 and SAFE2 as open-drain outputs, an external pullup resistor is required.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
MEASUREMENT VALUE (TEMPERATURE OR CURRENT)
HIGH THRESHOLD BUILT-IN HYSTERESIS
BUILT-IN HYSTERESIS LOW THRESHOLD
TIME ALARM OUTPUT OUTPUTCOMPARATOR MODE (ACTIVE LOW) OUTPUTINTERRUPT MODE (ACTIVE LOW)
FLAG REGISTER READ
FLAG REGISTER FLAG REGISTER READ READ
TIME
Figure 8. Window-Threshold-Mode Timing Diagram
In single-conversion mode (CKSEL = 11), the BUSY signal remains high until the ADC has completed the current conversion (not the entire scan, just the current conversion), the data has been moved into the FIFO, and the alarm limits for the channel have been checked (if enabled). In multiple-conversion mode (CKSEL = 01 or CKSEL = 00), the BUSY signal remains high until all channels have been scanned and the data from the final channel has been moved into the FIFO and checked for alarm limits (if enabled). In continuous-conversion mode (CONCONV = 1), the BUSY signal does not go high as a result of ADC conversions; however, BUSY does go high when CONCONV is removed and remains high until the current scan is complete and the ADC sequence halts. After commanding any of the DAC autocalibration components, wait for BUSY to go low before setting OSCPD to 1.
current is too high, and then to deassert when the temperature/current falls back to an appropriate level. ALARM asserts when SAFE1 and/or SAFE2 asserts. Program ALARM for output-comparator mode to stay asserted after an alarm condition until temperature/current levels are back below programmed thresholds. Program ALARM for output-interrupt mode to stay asserted after an alarm condition until the Flag register is read.
Alarm Modes
The MAX1385/MAX1386 contain several programmable modes for configuring outputs ALARM, SAFE1, and SAFE2 behavior. Window-threshold mode allows SAFE_ to assert when the temperature/current is too high or too low (outside the window). Hysteresis-threshold mode allows SAFE_ to assert when the temperature/
Window-Threshold Mode In window-threshold mode, ADC readings of current/temperature are compared to the configured current/temperature low/high thresholds that are programmed to cause an alarm condition. If an ADC reading falls out of the configured window and ALARM is configured for output-comparator mode, ALARM asserts until the current/temperature reading falls back into the window (past the built-in hysteresis). If an ADC reading falls out of the configured window and ALARM is configured for output-interrupt mode, ALARM asserts until the Flag register is read. Set the amount of built-in hysteresis from 8 LSBs to 64 LSBs (see the ALMSCFG (Read/Write) section). See Figures 7 and 8.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
HIGHEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR HIGH THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL ALARM OUTPUT ASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
HIGH THRESHOLD
LOW THRESHOLD
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE. WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ FOR ALARM TO BE DEASSERTED.
LOWEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR LOW THRESHOLD REGISTER)
Figure 9. Hysteresis-Threshold-Mode Diagram
Hysteresis-Threshold Mode In hysteresis-threshold mode, ADC readings of current/temperature are compared to the configured current/temperature low/high thresholds that are programmed to cause an alarm condition. If an ADC reading exceeds its respective configured threshold and ALARM is configured for output-comparator mode, ALARM asserts until the current/temperature reading falls back below its respective threshold. If an ADC reading exceeds its respective configured threshold and ALARM is configured for output-interrupt mode, ALARM asserts until the Flag register is read. See Figures 9 and 10.
TH1 and TH2 (Read/Write) Write to Channel 1 and Channel 2 High Temperature Threshold registers by sending the appropriate write command byte followed by data bits D15-D0 (see Table 3). Bits D15-D12 are don't care. Read channel 1 and channel 2 high-temperature thresholds by sending the appropriate read command byte. Channel 1 and Channel 2 Temperature Threshold registers are compared to temperature readings from the remote diode connected transistors. Temperature data is in two's-complement format and the LSB corresponds to 1/8C (see Figure 26 for the Temperature Transfer Function). TL1 and TL2 (Read/Write) Write to Channel 1 and Channel 2 Low-TemperatureThreshold registers by sending the appropriate write command byte followed by data bits D15-D0 (see Table 4). Bits D15-D12 are don't care. Read channel 1 and channel 2 low-temperature thresholds by sending the appropriate read command. Channel 1 and Channel 2 Temperature Threshold registers are compared to temperature readings from the remote diode connected transistors. Temperature data is in two's-complement format and the LSB corresponds to 1/8C (see Figure 26 for the Temperature Transfer Function).
Register Descriptions
Communicate with the MAX1385/MAX1386 through the I2C/SPI-compatible serial interface. Complete read and write operations consist of slave address bytes, command bytes, and data bytes. The following register descriptions cover the contents of command bytes and data bytes. See the Digital Serial Interface section for a detailed description of how to construct full read and write operations. All registers are volatile and are reset to default states upon removal of power. These default states are referred to as power-on reset (POR) states. All accessible MAX1385/MAX1386 registers are shown in Table 2.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Table 2. Register Listing (See Appendix: Recommended Power-Up Code Sequence section)
REGISTER DESCRIPTION Analog-to-Digital Conversion Channel 1 High-Current Threshold Channel 1 High-Temperature Threshold Channel 1 Low-Current Threshold Channel 1 Low-Temperature Threshold Channel 2 High-Current Threshold Channel 2 High-Temperature Threshold Channel 2 Low-Current Threshold Channel 2 Low-Temperature Threshold Coarse DAC1 High Wiper Input Coarse DAC1 Low Wiper Input Coarse DAC1 Write-Through High Wiper Input Coarse DAC1 Write-Through Low Wiper Input Coarse DAC2 High Wiper Input Coarse DAC2 Low Wiper Input Coarse DAC2 Write-Through High Wiper Input Coarse DAC2 Write-Through Low Wiper Input Device Configuration FIFO Memory Fine DAC1 Input Read Fine DAC1 Input Register with Autocalibration Fine DAC1 Input Without Autocalibration Fine DAC1 Write-Through Input with Autocalibration Fine DAC1 Write-Through Input Without Autocalibration Fine DAC2 Input Read Fine DAC2 Input Register with Autocalibration Fine DAC2 Input Without Autocalibration Fine DAC2 Write-Through Input with Autocalibration Fine DAC2 Write-Through Input Without Autocalibration Flag Hardware Alarm Configuration PGA Calibration Control Software Clear Software LDAC Software Shutdown Software Alarm Configuration MNEMONIC ADCCON IH1 TH1 IL1 TL1 IH2 TH2 IL2 TL2 HIWIPE1 LOWIPE1 THRUHI1 THRULO1 HIWIPE2 LOWIPE2 THRUHI2 THRULO2 DCFIG FIFO RDFINE1 FINECAL1 FINE1 FINECALTHRU1 FINETHRU1 RDFINE2 FINECAL2 FINE2 FINECALTHRU2 FINETHRU2 RDFLAG ALMHCFG PGACAL SCLR LDAC SSHUT ALMSCFG HEX COMMAND WRITE 62 24 20 26 22 2C 28 2E 2A 34 36 74 76 3A 3C 7A 7C 30 -- -- 38 50 78 52 -- 3E 54 7E 56 -- 60 4E 68 66 64 32 READ -- A4 A0 A6 A2 AC A8 AE AA B4 B6 B4 B6 BA BC BA BC B0 80 B8 -- -- -- -- BE -- -- -- -- EA E0 -- -- -- -- B2
MAX1385/MAX1386
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
MEASUREMENT VALUE (TEMPERATURE OR CURRENT)
HIGH THRESHOLD
LOW THRESHOLD
ALARM OUTPUT OUTPUTCOMPARATOR MODE (ACTIVE LOW) OUTPUTINTERRUPT MODE (ACTIVE LOW)
TIME
FLAG REGISTER READ
FLAG REGISTER READ
TIME
Figure 10. Hysteresis-Threshold-Mode Timing Diagram
Table 3. TH1 and TH2 (Read/Write)
D15 POR Bit Value (C) X X D14 X X D13 X X D12 X X D11 (MSB) 0 -256 D10 1 +128 D9 1 +64 D8 1 +32 D7 1 +16 D6 1 +8 D5 1 +4 D4 1 +2 D3 1 +1 D2 1 +0.5 D1 1 +0.25 D0 (LSB) 1 +0.125
X = Don't care.
IH1 and IH2 (Read/Write) Write to Channel 1 and Channel 2 High-CurrentThreshold registers by sending the appropriate write command byte followed by data bits D15-D0 (see Table 5). Bits D15-D12 are don't care. Read channel 1 and channel 2 high-current thresholds by sending the appropriate read command byte. Channel 1 and Channel 2 Current-Threshold registers are compared to ADC readings at PGAOUT1 and PGAOUT2. Use the following equation to find the required threshold code for a specified threshold current:
I THRESH = IDRAIN x RSENSE x AvPGA x 4096 VREFADC
where I DRAIN is the current threshold in amperes, RSENSE is the sense resistor, AvPGA is the voltage gain of the PGA, VREFADC is the ADC reference voltage, and I THRESH is the resulting threshold register value in decimal.
IL1 and IL2 (Read/Write) Write to Channel 1 and Channel 2 Low-CurrentThreshold registers by sending the appropriate write command byte followed by data bits D15-D0 (see Table 6). Bits D15-D12 are don't care. Read channel 1 and channel 2 low-current thresholds by sending the appropriate read command byte. Channel 1 and Channel 2 Low-Current Threshold registers are compared to ADC readings at PGAOUT1 and PGAOUT2.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 4. TL1 and TL2 (Read/Write)
D15 POR Bit Value (C) X X D14 X X D13 X X D12 X X D11 (MSB) 1 -256 D10 0 +128 D9 0 +64 D8 0 +32 D7 0 +16 D6 0 +8 D5 0 +4 D4 0 +2 D3 0 +1 D2 0 +0.5 D1 0 +0.25 D0 (LSB) 0 +0.125
X = Don't care.
Table 5. IH1 and IH2 (Read/Write)
D15 POR Bit Value X X D14 X X D13 X X D12 X X D11 (MSB) 1 -- D10 1 -- D9 1 -- D8 1 -- D7 1 -- D6 1 -- D5 1 -- D4 1 -- D3 1 -- D2 1 -- D1 1 -- D0 (LSB) 1 --
X = Don't care.
Table 6. IL1 and IL2 (Read/Write)
D15 POR Bit Value X X D14 X X D13 X X D12 X X D11 (MSB) 0 -- D10 0 -- D9 0 -- D8 0 -- D7 0 -- D6 0 -- D5 0 -- D4 0 -- D3 0 -- D2 0 -- D1 0 -- D0 (LSB) 0 --
X = Don't care.
Use the following equation to find the required threshold code for a specified threshold current: I THRESH = IDRAIN x RSENSE x AvPGA x 4096 VREFADC
where I DRAIN is the current threshold in amperes, RSENSE is the sense resistor, AvPGA is the voltage gain of the PGA, VREFADC is the ADC reference voltage, and I THRESH is the resulting threshold register value in decimal.
of each clock mode. Set REFADC1 and REFADC0 to select external/internal reference for the ADC (see Table 7c). Set REFDAC1 and REFDAC0 to select external/internal reference for both DACs (see Table 7d). When mode 11 is selected, the external capacitor that is connected to the REFADC is charged by a resistor with a typical value of 400k. This time constant needs to be allowed for powering up the reference. Avoid leakage paths to REFADC.
DCFIG (Read/Write)
Select PGA gain settings, clock modes, and DAC and ADC reference modes by sending the appropriate write command byte followed by data bits D15-D0 (see Table 7). Bits D15-D10 are don't care. Read the Device Configuration register by sending the appropriate read command byte. Program PG2SET1 and PG2SET0 to set channel 2's current-sense amplifier gain (see Table 7a). Program PG1SET1 and PG1SET0 to set channel 1's current-sense amplifier gain (see Table 7a). Set CKSEL1 and CKSEL0 to determine the conversion and acquisition timing clock modes (see Table 7b). See the ADC Clock Modes section for a functional description
ALMSCFG (Read/Write) The Software Alarm Configuration register controls the behavior of outputs SAFE1, SAFE2, and ALARM. Write to the Software Alarm Configuration register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 8). Bits D15-D12 are don't care. Read the Software Alarm Configuration register by sending the appropriate command byte.
Set ALMSCLR to 1 to immediately set all temperature/ current threshold registers to their POR state. In addition, temperature-/current-related bits of the Flag register are also reset to their POR state. The ALMSCLR resets to 0 immediately after a write. Set ALARMCMP to 1 to enable output-comparator mode for ALARM and to 0 to enable output-interrupt mode for ALARM (see the
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 7. DCFIG (Read/Write)
BIT NAME X PG2SET1 PG2SET0 PG1SET1 PG1SET0 CKSEL1 CKSEL0 REFADC1 REFADC0 REFDAC1 REFDAC0 DATA BIT D15-D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POR X 0 0 0 0 0 0 0 0 0 0 FUNCTION Don't care PGA 2 gain-setting PGA 2 gain-setting PGA 1 gain-setting PGA 1 gain-setting Clock mode and CNVST configuration Clock mode and CNVST configuration ADC reference select ADC reference select DAC reference select DAC reference select 0 0 Internal
Table 7a. Gain-Setting Modes
PG_SET1 0 0 1 PG_SET0 0 1 X FUNCTION PGA_ gain of 2 PGA_ gain of 10 PGA_ gain of 25
X = Don't care.
Table 7b. Clock Modes
CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/ SAMPLING Internally timed acquisitions and conversions. Conversions started by a write to the Analogto-Digital Conversion register or setting the CONCONV bit. Internally timed acquisitions and conversions. Conversions begin with a high-to-low transition at CNVST. Reserved. Do not use. Externally timed acquisitions by CNVST. Conversions internally timed.
Alarm Modes section). Setting ALARMCMP does not affect SAFE1 and SAFE2 outputs. Program ALARMHYST1 and ALARMHYST0 to set the amount of built-in hysteresis used in window-threshold mode. See the ALARM Output and SAFE1/SAFE2 Outputs sections for a description of the relationship between ALARM and SAFE1 and SAFE2. Set TALARM2 to 1 to allow channel 2 temperature measurements to control the state of SAFE2 and ALARM based on channel 2 temperature thresholds. Set TWIN2 to 0 to enable hysteresis-threshold mode and to 1 to enable windowthreshold mode for channel 2 temperature measurements (see the Alarm Modes section). Set IALARM2 to 1 to allow channel 2 current measurements to control the state of SAFE2 and ALARM based on channel 2 current thresholds. Set IWIN2 to 0 to enable hysteresis-threshold mode and to 1 to enable windowthreshold mode for channel 2 current measurements. Set TALARM1 to 1 to allow channel 1 temperature measurements to control the state of SAFE1 and ALARM based on channel 1 temperature thresholds. Set TWIN1 to 0 to enable hysteresis-threshold mode and to 1 to enable window-threshold mode for channel 1 temperature measurements (see the Alarm Modes section). Set IALARM1 to 1 to allow channel 1 current measurements to control the state of SAFE1 and ALARM based on channel 1 current thresholds. Set IWIN1 to 0 to enable hysteresis-threshold mode and to 1 to enable windowthreshold mode for channel 1 current measurements. HIWIPE1 and HIWIPE2 (Read/Write) Write to the Coarse DAC1/DAC2 High Wiper Input register by sending the appropriate write command byte
30
0
1
Internal
1
0
--
1
1
Internal
Table 7c. ADC Reference Selection
REFADC1 0 1 REFADC0 X 0 DESCRIPTION External. Bypass REFADC with a 0.1F capacitor to AGND. Internal. Leave REFADC unconnected. Internal. Connect a 0.1F capacitor to REFADC for better noise performance.
1
1
X = Don't care.
followed by data bits D15-D0 (see Table 9). Bits D14-D8 are don't care. Read the Coarse DAC1/DAC2 High Wiper Input register by sending the appropriate read command byte. The DAC output is not updated until an LDAC command is issued, at which point the
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Table 7d. DAC Reference Selection
REFDAC1 0 1 REFDAC0 X 0 DESCRIPTION External. Bypass REFDAC with a 0.1F capacitor to AGND. Internal. Leave REFDAC unconnected. Internal. Connect a 0.1F capacitor to REFDAC for extra decoupling and better noise performance.
Table 12). Bits D15-D8 are reserved and must be set to 0. Bits D7-D3 are don't care. Set FIRSTB to 1 to enable tracking-calibration mode, and to 0 to enable acquisition-calibration mode. During an offset calibration trial, for either mode, the corresponding PGAOUT_ is put into hold, which produces a pedestal error for 67s typically and BUSY is set to 1. In acquisition mode, the calibration routine operates continuously, first on channel 1 and then on channel 2, until the channel-input offset voltage error has been reduced to within 50V. The time taken for both channels to complete acquisition depends upon the initial channel offset voltage error but should never be longer than 112ms. In tracking mode, a pair of offset calibration trials, first on channel 1 and then on channel 2, are made each time DOCAL is set to 1 or every 20ms if the SELFTIME bit is set to 1. To reject noise, the offset trim DAC code (not shown in the Functional Diagram) only increments or decrements after the results of 16 calibration trials have been averaged. Set FIRSTB to 0 and DOCAL to 1 to initiate an acquisition calibration. Acquisition must be done before tracking the first time a PGA calibration is commanded. Set FIRSTB to 1, DOCAL to 1, and SELFTIME to 0 to trigger an offset calibration trial on PGA1 and PGA2. At the end of the routine, DOCAL returns to 0. Set FIRSTB to 1, DOCAL to 1 (optional to trigger calibration once immediately before SELFTIME starts periodic calibrations), and SELFTIME to 1, just once, to trigger periodic offset-calibration trials (approximately every 20ms). Set SELFTIME to 0 to halt the periodic calibration.
MAX1385/MAX1386
1
1
X = Don't care.
DAC input register is transferred to the appropriate DAC output register. Automatic calibration of the high wiper is initiated if the HCAL bit in the DAC input register is set to 1 when the appropriate LDAC command is issued.
LOWIPE1 and LOWIPE2 (Read/Write) Write to the Coarse DAC1/DAC2 Low Wiper Input register by sending the appropriate command byte followed by data bits D15-D0 (see Table 10). Bits D14-D8 are don't care. Read the Coarse DAC1/DAC2 Low Wiper Input register by sending the appropriate read command byte. The DAC output is not updated until an LDAC command is issued, at which point the DAC input register is transferred to the appropriate DAC output register. Automatic calibration of the low wiper is initiated if the LCAL bit in the DAC input register is set to 1 when the appropriate LDAC command is issued. FINECAL1 and FINECAL2 (Write) Write to the Fine DAC1/DAC2 Input register with autocalibration by sending the appropriate write command byte followed by data bits D15-D0 (see Table 11). Bits D15-D10 are don't care. A write to these registers triggers the autocalibration but does not automatically update the output of the DAC. Write to the Software LDAC register (LDAC) to transfer the Fine DAC Input register contents to the Fine DAC Output register, thereby updating the output of the DAC. POR contents for these registers are all zeros. Read the DAC input register values written to Fine DAC1 and DAC2 Input registers through the Fine DAC1/DAC2 Input Read register. These read registers contain the latest user-write to any Fine DAC1 or Fine DAC2 Input Read register and do not contain autocalibration-corrected values. PGACAL (Write) Write to the PGA Calibration Control register to calibrate PGA1 and PGA2 internal amplifiers. Write to the PGA Calibration Control register by sending the appropriate write command byte followed by data bits D15-D0 (see
FINE1 and FINE2 (Write) Write to the Fine DAC1/DAC2 Input register without autocalibration by sending the appropriate write command byte followed by data bits D15-D0 (see Table 13). Bits D15-D10 are don't care. A write to these registers does not trigger the autocalibration and does not automatically update the output of the DAC. Write to the Software LDAC register (LDAC) to transfer the DAC input register contents to the Fine DAC Output register, thereby updating the output of the fine DAC. POR contents for these registers are all zeros. Read the DAC input register values written to Fine DAC1 and DAC2 Input registers through the Fine DAC1/DAC2 Input Read register. These read registers contain the latest user-write to any Fine DAC1 or Fine DAC2 Input Read register and do not contain autocalibration corrected values. FINETHRU1 and FINETHRU2 (Write) Write to the Fine DAC1/DAC2 Write-Through Input register without autocalibration by sending the appropriate write command byte followed by data bits D15-D0 (see
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 8. ALMSCFG (Read/Write)
BIT NAME X ALMSCLR ALARMCMP ALARMHYST1 ALARMHYST0 TALARM2 TWIN2 IALARM2 IWIN2 TALARM1 TWIN1 IALARM1 IWIN1 DATA BIT D15-D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POR X 0 0 0 0 0 0 0 0 0 0 0 0 Don't care 1 = Temp/current thresholds set to POR state 0 = Temp/current thresholds unaffected 1 = ALARM in output-comparator mode 0 = ALARM in output-interrupt mode Thresholds hysteresis (ALARMHYST1 is MSB) 00 = 8 LSBs of hysteresis 01 = 16 LSBs of hysteresis 10 = 32 LSBs of hysteresis 11 = 64 LSBs of hysteresis 1 = SAFE2 and ALARM dependent on channel 2 temperature 0 = SAFE2 and ALARM not dependent on channel 2 temperature 1 = Channel 2 temperature thresholds are in window-threshold mode 0 = Channel 2 temperature thresholds are in hysteresis-threshold mode 1 = SAFE2 and ALARM dependent on channel 2 current 0 = SAFE2 and ALARM not dependent on channel 2 current 1 = Channel 2 current thresholds are in window-threshold mode 0 = Channel 2 current thresholds are in hysteresis-threshold mode 1 = SAFE1 and ALARM dependent on channel 1 temperature 0 = SAFE1 and ALARM not dependent on channel 1 temperature 1 = Channel 1 temperature thresholds are in threshold-window mode 0 = Channel 1 temperature thresholds are in hysteresis-threshold mode 1 = SAFE1 and ALARM dependent on channel 1 current 0 = SAFE1 and ALARM not dependent on channel 1 current 1 = Channel 1 current thresholds are in window-threshold mode 0 = Channel 1 current thresholds are in hysteresis-threshold mode FUNCTION
X = Don't care.
Table 9. HIWIPE1 and HIWIPE2 (Read/Write)
BIT NAME HCAL -- -- DATA BIT D15 D14-D8 D7-D0 POR 1 X 0000 0000 1 = High wiper autocalibration. 0 = No high wiper autocalibration. Don't care. 8-bit coarse high wiper DAC input code. D7 is the MSB. FUNCTION
Table 14). Bits D15-D10 are don't care. A write to these registers does not trigger the autocalibration but immediately updates the output of the DAC by transferring the DAC input register to the DAC output register (writing through the input register). POR contents for these registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers through the Fine DAC1/DAC2 Input Read register. These read registers contain the latest user write to any Fine DAC1 or Fine DAC2 Input Read register and do not contain autocalibration corrected values.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 10. LOWIPE1 and LOWIPE2 (Read/Write)
BIT NAME LCAL -- -- DATA BIT D15 D14-D8 D7-D0 POR 1 X 0000 0000 1 = Low wiper autocalibration. 0 = No low wiper autocalibration. Don't care. 8-bit coarse low wiper DAC input code. D7 is the MSB. FUNCTION
ALMHCFG (Read/Write) The Hardware Alarm Configuration register controls SAFE1, SAFE2, and ALARM outputs. Write to the Hardware Alarm Configuration register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 15). Bits D15-D8 are don't care. Read the Hardware Alarm Configuration register by sending the appropriate read command byte. Set SETSAFE1 to 1 to immediately force SAFE1 active. This is especially useful when SAFE1 is connected to OPSAFE1, giving the user software control over shutting down the LDMOS transistor. Set SETSAFE1 to 0 for normal operation. SETSAFE2 has the same functionality as SETSAFE1 but for channel 2.
Set ALARMPOL to 1 to configure ALARM active-low. Set it to 0 to configure ALARM active-high. Set ALARMOPN to 1 to configure ALARM open-drain. Set it to 0 to configure ALARM push-pull. Set SAFE1POL to 1 to configure SAFE1 for active-low, and to 0 for active-high. Set SAFE2POL to 1 to configure SAFE2 for active-low, and to 0 for active-high. Set SAFE1OPN to 1 to configure SAFE1 for open-drain, and to 0 for push-pull. Set SAFE2OPN to 1 to configure SAFE2 for open-drain, and to 0 for push-pull. When connecting SAFE1 and SAFE2 outputs to OPSAFE1 and OPSAFE2 inputs, configure the device as follows: 1) Set SAFE1POL and SAFE2POL to 0s.
Table 11. FINECAL1 and FINECAL2 (Write)
DATA BIT D15-D10 D9-D0 POR X 00 0000 0000 FUNCTION Don't care. 10-bit fine DAC input code. D9 is the MSB.
2) Set SAFE1OPN and SAFE2OPN to 0s. This ensures that when SAFE1 and SAFE2 are asserted, and connected to OPSAFE1 and OPSAFE2, the LDMOS transistors are shut off.
ADCCON (Write) The Analog-to-Digital Conversion register selects which inputs to the ADC are converted. Write to the Analog-toDigital Conversion register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 16). Bits D15-D12 are don't care. Bits D11-D8 are reserved bits and need to be set to 0. Read the results of the conversions in the FIFO by sending the appropriate read command byte. See the ADC Description section for a complete description of the ADC. Set CONCONV to 1 to convert selected inputs to the ADC continuously and to 0 to convert selected inputs to the ADC only once. Set ADCSEL2 to 1 to select voltages at ADCIN2 to be converted. Set IEXT2 to 1 to select voltages at PGAOUT2 to be converted. Set
Table 12. PGACAL (Write)
BIT NAME RESERVED X FIRSTB DOCAL SELFTIME DATA BIT D15-D8 D7-D3 D2 D1 D0 RESET STATE 0 X 0 0 0 Reserved. Set to 0. Don't care. 1 = Tracking calibration mode. 0 = Acquisition calibration mode. 1 = Initiate the calibration defined by FIRSTB (one time). 0 = Do not initiate a calibration. 1 = Initiate periodic calibrations defined by FIRSTB (every 15ms). 0 = Stop periodic calibrations. FUNCTION
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
TEXT2 to 1 to select the temperature at external diode 2 to be converted. Set ADCSEL1 to 1 to select voltages at ADCIN1 to be converted. Set IEXT1 to 1 to select voltages at PGAOUT1 to be converted. Set TEXT1 to 1 to select the temperature at external diode 1 to be converted. Set TINT to 1 to select the internal temperature of the MAX1385/MAX1386 to be converted. During continuous conversions (CONCONV = 1), the ADC does not trigger the BUSY signal. When CONCONV is set to 0, the current scan (not just the current conversion) is completed and the ADC waits for the next command. During continuous conversions, the FIFO overflows if the user does not read it quickly enough. When the FIFO overflows, it contains a mixture of old and new conversion results (see the RDFLAG (Read) section). Continuous conversion mode is only available in clock modes 00 and 01.
Table 13. FINE1 and FINE2 (Write)
DATA BIT D15-D10 D9-D0 POR X 00 0000 0000 FUNCTION Don't care. 10-bit fine DAC input code. D9 is the MSB.
Table 14. FINETHRU1 and FINETHRU2 (Write)
DATA BIT D15-D10 D9-D0 POR X 00 0000 0000 FUNCTION Don't care. 10-bit fine DAC input code. D9 is the MSB.
SSHUT (Write) The Software Shutdown register shuts down all internal blocks at once or the DAC, ADC, and PGA blocks individually. Write to the Software Shutdown register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 17). Bits D15-D8 and D6, D5, and D4 are don't care. Set FULLPD to 1 to shut down all internal blocks and reduce the AVDD supply current to 0.2A. FULLPD is set to 1 at power-up. To change to normal power mode, write two commands to the Software Shutdown register. The first command sets FULLPD to 0 (other bits in the Software Shutdown register are ignored). A second command is needed to activate any internal blocks. FULLPD overrides all other shutdown bits; however, all shutdown bits retain their data when FULLPD is set to 1. This means that if DAC1 and PGA1 are shut down before FULLPD is set to 1, they remain shut down after FULLPD is set to 0 again.
Set FBGON to 1 to force the internal bandgap reference to be powered at all times. Set FBGON to 0 to transfer power-down control of the internal reference to the ADC. In the event of DAC1PD or DAC2PD being set to 0, the internal bandgap is forced on. Set OSCPD to 1 to shut down the internal oscillator. When the oscillator is shut down, the ADC ceases conversions and internal PGA calibration halts. Any interface command restarts the oscillator and allows the system to resume from where it left off. Set DAC2PD to 1 to shut down DAC2 and PGA2. Set DAC1PD to 1 to shut down DAC1 and PGA1. DAC1PD and DAC2PD power down the individual blocks regardless of additional commands; however, writes are still permitted to the DACs and PGAs. For maximum accuracy, do not command a DAC calibration while a DAC is powered down or powering up.
34
LDAC (Write) The Software LDAC register controls the loading of the DAC output registers with values from DAC input registers, allowing the user to update several changes to the DAC all at once (see Table 18). Write to the Software LDAC register by sending the appropriate write command byte followed by data bits D15-D0. Bits D15-D6 are don't care. Any bit set to 1 in the Software LDAC register is immediately set to 0 thereafter.
Table 15. ALMHCFG (Read/Write)
BIT NAME X SETSAFE1 DATA BIT D15-D8 D7 POR X 0 FUNCTION Don't care 1 = Force SAFE1 active immediately 0 = Normal operation 1 = Force SAFE2 active immediately 0 = Normal operation 1 = ALARM is active-low 0 = ALARM is active-high 1 = ALARM is open-drain 0 = ALARM is push-pull 1 = SAFE1 is active-low 0 = SAFE1 is active-high 1 = SAFE1 is open-drain 0 = SAFE1 is push-pull 1 = SAFE2 is active-low 0 = SAFE2 is active-high 1 = SAFE2 is open-drain 0 = SAFE2 is push-pull
SETSAFE2
D6
0
ALARMPOL ALARMOPN SAFE1POL SAFE1OPN SAFE2POL SAFE2OPN
D5 D4 D3 D2 D1 D0
0 0 0 0 0 0
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 16. ADCCON (Write)
BIT NAME X Reserved CONCONV ADCSEL2 IEXT2 TEXT2 ADCSEL1 IEXT1 TEXT1 TINT DATA BIT D15-D12 D11-D8 D7 D6 D5 D4 D3 D2 D1 D0 POR X 0 0 0 0 0 0 0 0 0 Don't care Reserved; set these bits to 0 1 = Continuous conversions (repeated scans) 0 = Noncontinuous conversions (one scan) 1 = Select voltages at ADCIN2 to be converted 0 = Do not select voltages at ADCIN2 to be converted 1 = Select voltages at PGAOUT2 to be converted 0 = Do not select voltages at PGAOUT2 to be converted 1 = Select temperature at remote diode 2 to be converted 0 = Do not select temperature at remote diode 2 to be converted 1 = Select voltages at ADCIN1 to be converted 0 = Do not select voltages at ADCIN1 to be converted 1 = Select voltages at PGAOUT1 to be converted 0 = Do not select voltages at PGAOUT1 to be converted 1 = Select temperature at remote diode 1 to be converted 0 = Do not select temperature at remote diode 1 to be converted 1 = Select internal temperature of device to be converted 0 = Do not select internal temperature of device to be converted FUNCTION
Set FINECH2 to 1 to load the fine DAC2 output register with the latest write to DAC2 input registers FINE2 or FINECAL2. This means that if FINE2 is written to after FINECAL2, FINE2 is sent to the fine DAC2 output register (no calibration code) when FINECH2 is set to 1. Set HIGHCH2 to 1 to load DAC input register HIWIPE2 into the Coarse DAC2 High Wiper register. Autocalibration of the DAC2 high wiper occurs if the HCAL bit in HIWIPE2 is set to 1. Set LOWCH2 to 1 to load DAC input register LOWIPE2 into the Coarse DAC2 Low Wiper register. Autocalibration of the DAC2 low wiper occurs if the LCAL bit in LOWIPE2 is set to 1. Set FINECH1 to 1 to load the fine DAC1 output register with the latest write to DAC input registers FINE1 or FINECAL1. If FINECAL1 is written to after FINE1, FINECAL1 is sent to the fine DAC1 output register (with calibration code) when FINECH1 is set to 1. Set HIGHCH1 to 1 to load DAC input register HIWIPE1 into the Coarse DAC1 output register. Autocalibration of the DAC1 high wiper occurs if the HCAL bit in HIWIPE1 is set to 1. Set LOWCH1 to 1 to load DAC input register LOWIPE1 into the coarse DAC1 output register. Autocalibration of the DAC1 low wiper occurs if the LCAL bit in LOWIPE1 is set to 1.
SCLR (Write) Write to the Software Clear register to reset the DACs and FIFO to their POR states (see Table 19). Write to the Software Clear register by sending the appropriate write command byte followed by data bits D15-D0. Bits D15-D10 are don't care. A write to bits D5-D0 in the Software Clear register immediately changes the appropriate DAC output to its power-on state (regardless of LDAC). To reset all registers at once, set FULLRESET to 0 and ARMRESET to 1. Next set FULLRESET to 1 and ARMRESET to 0. This 2-byte reset operation protects the registers from being fully reset by inadvertent user writes. After a full reset, the device is in shutdown mode and the SSHUT register needs to be written to for full operation. Set CLFIFO to 1 to clear the entire 15-word FIFO and FIFO-associated flag bits in the Flag register. Set HIGHCL2 to 1 to reset the Coarse DAC2 High Wiper Output and Input registers to their POR states. Set LOWCL2 to 1 to reset the coarse DAC2 High Wiper Output and Input registers to their POR states. Set FINECL1 to 1 to reset Fine DAC1 Output and Input registers to their POR states. Set HIGHCL1 to 1 to reset the Coarse DAC1 High Wiper Output and Input registers to their POR states. Set LOWCL1 to 1 to reset the
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 17. SSHUT (Write)
BIT NAME X FULLPD X FBGON OSCPD DAC2PD DAC1PD DATA BIT D15-D8 D7 D6, D5, D4 D3 D2 D1 D0 POR X 1 X 0 0 1 1 Don't care 1 = Shut down all internal blocks 0 = Do not shut down all internal blocks Don't care 1 = Force internal bandgap reference to be powered always 0 = Let the ADC control power-down of the internal reference 1 = Shut down the internal oscillator 0 = Do not shut down the internal oscillator 1 = Power down DAC2 0 = Do not power down DAC2 1 = Power down DAC1 0 = Do not power down DAC1 FUNCTION
Table 18. LDAC (Write)
BIT NAME X FINECH2 HIGHCH2 LOWCH2 FINECH1 HIGHCH1 LOWCH1 DATA BIT D15-D6 D5 D4 D3 D2 D1 D0 POR X N/A N/A N/A N/A N/A N/A Don't care 1 = Update fine DAC2 with FINE2 or FINECAL2 0 = Do not update DAC2 1 = Update coarse DAC2 with HIWIPE2 0 = Do not update DAC2 1 = Update coarse DAC2 with LOWIPE2 0 = Do not update DAC2 1 = Update fine DAC1 with FINE1 or FINECAL1 0 = Do not update DAC1 1 = Update coarse DAC1 with HIWIPE1 0 = Do not update DAC1 1 = Update coarse DAC1 with LOWIPE1 0 = Do not update DAC1 FUNCTION
Coarse DAC1 Low Wiper Output and Input registers to their POR states. Set FINECL2 to 1 to reset Fine DAC2 Output and Input registers to their POR states.
Wiper Input register by sending the appropriate read command byte.
THRUHI1 and THRUHI2 (Read/Write) Write to the Coarse DAC1/DAC2 Write-Through High Wiper Input register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 20). Bits D15-D8 are don't care. Writing to one of these registers automatically writes through to the appropriate DAC output register, thereby updating the DAC output immediately. Writing to one of these registers does not trigger automatic high wiper calibration. Read the Coarse DAC1/DAC2 Write-Through High
36
THRULO1/THRULO2 (Read/Write) Write to the Coarse DAC1/DAC2 Write-Through Low Wiper Input register by sending the appropriate write command byte followed by data bits D15-D0 (see Table 21). Bits D15-D8 are don't care. Writing to one of these registers automatically writes through to the appropriate DAC output register, thereby updating the DAC output immediately. Writing to one of these registers does not trigger automatic low wiper calibration. Read the Coarse DAC1/DAC2 Write-Through Low
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 19. SCLR (Write)
BIT NAME X FULLRESET ARMRESET X CLFIFO HIGHCL2 LOWCL2 FINECL1 HIGHCL1 LOWCL1 FINECL2 DATA BIT D15-D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POR X N/A 0 X N/A N/A N/A N/A N/A N/A N/A Don't care Full reset of all DAC registers is a two write operation: 1) FULLRESET = 0, ARMRESET = 1 2) FULLRESET = 1, ARMRESET = 0 Don't care 1 = Clear FIFO and FIFO flag bits 0 = Do not clear FIFO or FIFO flag bits 1 = Reset coarse DAC2 high wiper to its POR state 0 = Do not reset coarse DAC2 high wiper to its POR state 1 = Reset coarse DAC2 low wiper to its POR state 0 = Do not reset coarse DAC2 low wiper to its POR state 1 = Reset fine DAC1 to its POR state 0 = Do not reset fine DAC1 to its POR state 1 = Reset coarse DAC1 high wiper to its POR state 0 = Do not reset coarse DAC1 high wiper to its POR state 1 = Reset coarse DAC1 high wiper to its POR state 0 = Do not reset coarse DAC1 high wiper to its POR state 1 = Reset fine DAC2 to its POR state 0 = Do not reset fine DAC2 to its POR state FUNCTION
Wiper Input register by sending the appropriate read command byte.
the FIFO when the FIFO is empty results in the current contents of the Flag read register to be sent.
FINETHRUCAL1 and FINETHRUCAL2 (Write) Write to the Fine DAC1/DAC2 Write-Through Input register with autocalibration by sending the appropriate write command byte followed by data bits D15-D0 (see Table 22). Bits D15-D10 are don't care. A write to these registers not only triggers the autocalibration but immediately updates the output of the DAC by transferring the DAC input register with correction code to the Fine DAC output register. POR contents for these registers are all zeros. Read the DAC Input register values written to Fine DAC1 and DAC2 Input registers through the Fine DAC1/DAC2 Input Read register. These read registers contain the latest user-write to any Fine DAC1 or Fine DAC2 Input register and do not contain autocalibration-corrected values. FIFO (Read) Read the oldest result in the FIFO by sending the appropriate read command byte and reading out data bits D15-D0 (see Table 23). Bits D15-D12 are channel tag bits that indicate the source of the conversion. Bits D11-D0 contain the conversion result. Reading from
RDFINE1 and RDFINE2 (Read) Read the Fine DAC1/DAC2 Input Read register by sending the appropriate read command byte and reading out data bits D15-D0 (see Table 24). Data contains the last write to any Fine DAC1/DAC2 Input registers and does not contain autocalibration-corrected values. RDFLAG (Read) The Flag register contains important system information regarding ADC/FIFO status and alarm conditions. Read the Flag register by sending the appropriate read command byte and reading out data bits D15-D0 (see Table 25). Bits D15-D12 are don't care. ADCBUSY is set to 1 when the ADC is busy, an ALARM value is being checked, or the ADC results are being loaded into the FIFO. ADCBUSY is set to 0 when the ADC has completed all the conversions in the current scan.
ALUBUSY is set to 1 when the ALU is busy and set to 0 when it is not. ALUBUSY is set to 1 for 134s at powerup for initialization. FIFOEMP is set to 1 when the FIFO is empty and set to 0 when the FIFO contains data. Writing to the appropriate bit in the Software Clear register empties the FIFO and sets the FIFOEMP bit to 1.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
FIFOOVER is set to 1 when the FIFO overflows. FIFOOVER is set to 0 after reading the Flag register. All threshold-related bits in the Flag register can be cleared at once by writing to the ALMSCLR bit in the Software Alarm Configuration register (see the ALMSCFG (Read/Write) section). HIGHI2 is set to 1 when the channel 2 current exceeds its high threshold. HIGHI2 resets to 0 after reading the Flag register. LOWI2 is set to 1 when the channel 2 current drops below its low threshold. LOWI2 resets to 0 after reading the Flag register. HIGHT2 is set to 1 when the channel 2 temperature measurement exceeds its high threshold. HIGHT2 resets to 0 after reading the Flag register. The LOWT2 is set to 1 when the channel 2 temperature measurement drops below its low threshold. LOWT2 resets to 0 after reading the Flag register. HIGHI1 is set to 1 when the channel 1 current exceeds its high threshold. HIGHI1 resets to 0 after reading the Flag register. LOWI1 is set to 1 when the channel 1 current drops below its low threshold. LOWI1 resets to 0 after reading the Flag register. HIGHT1 is set to 1 when the channel 1 temperature measurement exceeds its high threshold. HIGHT1 resets to 0 after reading the Flag register. LOWT1 is set to 1 when the channel 1 temperature measurement drops below its low threshold. LOWT1 resets to 0 after reading the Flag register.
Table 20. THRUHI1 and THRUHI2 (Read/Write)
DATA BIT D15-D8 D7-D0 POR X 0000 0000 Don't care. 8-bit coarse high wiper DAC input code. D7 is the MSB. FUNCTION
Table 21. THRULO1 and THRULO2 (Read/Write)
DATA BIT D15-D8 D7-D0 POR X 0000 0000 Don't care. 8-bit coarse high wiper DAC input code. D7 is the MSB. FUNCTION
Table 22. FINETHRUCAL1 and FINETHRUCAL2 (Write)
DATA BIT D15-D10 D9-D0 POR X 00 0000 0000 FUNCTION Don't care. 10-bit fine DAC input code. D9 is the MSB.
Digital Serial Interface
The MAX1385/MAX1386 contain an I2C-/SPI-compatible serial interface for configuration. Connect the modeselect input, SEL, to DGND to select I2C mode. In I2C mode, the MAX1385/MAX1386 provide address inputs A0 to A2 to allow eight devices to be connected on the same bus (see the Slave Address Byte section). Connect SEL to DVDD to select SPI mode. In SPI mode, drive A0/CSB low to select the device. The MAX1385/ MAX1386 support fast (400kHz) and high-speed (1.7MHz or 3.4MHz) data-transfer modes. Data transfers occur in 8-bit bytes with acknowledge (ACK) or not-acknowledge (NACK) bits following each byte. The MAX1385/ MAX1386 are permanent slaves and do not generate their own clock signals. Figure 11 shows the various read/write formats.
Write Format Use the following sequence to write a single word (see Figure 11): 1) After generating a START condition (S or Sr), address the MAX1385/MAX1386 by sending the appropriate slave address byte with its corresponding R/W bit set to zero (see the Slave Address Byte section). The MAX1385/MAX1386 answer with an ACK bit (see the Acknowledge Bits section).
38
2) Send the appropriate write command byte (see the Command Byte section). The MAX1385/MAX1386 answer with an ACK bit. 3) Send the most significant 8-bit section of the 16-bit data word, sending the MSBs first (see the Data Bytes section). The MAX1385/MAX1386 answer with an ACK bit. 4) Send the least significant 8-bit section of the 16-bit data word, sending the MSBs first. The MAX1385/ MAX1386 answer with an ACK bit. 5) Generate a (repeated) START or STOP condition (Sr or P). To write to a block of registers, use the same steps as above but repeat steps 2, 3, and 4 without any START, STOP, or repeated START conditions (Sr). Finish the block write by generating a STOP condition.
Read Format All read operations can begin with a Sr as well as an S condition. One type of read is a 5-byte operation, one is a 3-byte operation, and the other is a continuous read operation. The 5-byte operation reads from the register address contained in one of the 5 bytes sent. The 3byte operation reads from the last register address accessed. Use the following 5-byte sequence to read
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 23. FIFO (Read)
D15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D14 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D13 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DATA BITS D12 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D11 MSB MSB MSB MSB MSB MSB -- -- -- -- -- -- -- MSB BITS D11-D0 CONTAIN THE CONVERSION RESULT MSB D0 LSB LSB LSB LSB LSB LSB LSB -- -- -- -- -- -- -- LSB CONVERSION ORIGIN Internal temperature sensor Channel 1 external temperature Channel 1 drain current (PGAOUT1) ADCIN1 Channel 2 external temperature Channel 2 drain current (PGAOUT2) ADCIN2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Conversion may be corrupted. This occurs only when arriving data causes the FIFO to overflow at the same time data is being read out. Empty FIFO. The current value of the Flag register is provided in place of the FIFO data.
1
1
1
1
MSB
LSB
16 bits of data from a MAX1385/MAX1386 register (see Figure 11): 1) After generating a START condition (S or Sr), address the MAX1385/MAX1386 by sending the appropriate slave address byte and its corresponding R/W bit set to a 0 (see the Slave Address Byte section). The MAX1385/MAX1386 then answer with an ACK bit (see the Acknowledge Bits section). 2) Send the appropriate read command byte (see the Command Byte section). The MAX1385/MAX1386 answer with an ACK bit. 3) After generating a repeated START condition (Sr), address the MAX1385/MAX1386 once more by sending the appropriate slave address byte and its R/W bit set to 1. The MAX1385/MAX1386 answer with an ACK bit. 4) The MAX1385/MAX1386 transmit the most significant 8-bit data byte of the 16-bit data word with the MSB first. Afterwards, the master needs to send an ACK bit. 5) The MAX1385/MAX1386 transmit the least significant 8-bit byte of the 16-bit word with the MSB first.
Table 24. RDFINE1 and RDFINE2 (Read)
DATA BITS D15-D10 D9-D0 POR X 00 0000 0000 FUNCTION Don't care. 10-bit fine DAC input code. D9 is the MSB.
6) The master issues a NACK bit and then generates a repeated START or STOP condition (Sr or P). Continue to poll the current register or read multiple words (e.g., empty FIFO of several conversion results) by omitting step 6 and keep issuing ACK bits after each data byte. Use the following 3-byte sequence to read 16 bits of data from the last accessed MAX1385/ MAX1386 register: 1) After generating a START condition (S or Sr), address the MAX1385/MAX1386 by sending the appropriate 7-bit slave address byte and its corresponding R/W bit set to 1 (see the Slave Address Byte section). The MAX1385/MAX1386 then answer with an ACK bit (see the Acknowledge Bits section).
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39
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
WRITE WORD FORMAT S OR Sr ADDRESS 7 BITS R/W 0 ACK WRITE COMMAND 8 BITS ACK DATA 8 BITS (MSB) ACK DATA 8 BITS (LSB) ACK Sr OR P
WRITE BLOCK FORMAT S OR Sr ADDRESS 7 BITS R/W 0 ACK WRITE COMMAND 8 BITS ACK DATA 8 BITS (MSB) ACK DATA 8 BITS (LSB) ACK Sr OR P
N 3-BYTE SEQUENCES (S, Sr, AND P NOT NEEDED) 5-BYTE READ S OR Sr ADDRESS 7 BITS R/W 0 ACK READ COMMAND 8 BITS ACK Sr ADDRESS 7 BITS R/W 1 ACK DATA 8 BITS (MSB) ACK DATA 8 BITS (LSB) NACK Sr OR P
3-BYTE READ S OR Sr ADDRESS 7 BITS R/W 1 ACK DATA 8 BITS (MSB) ACK DATA 8 BITS (LSB) NACK Sr OR P
Figure 11. Read/Write Formats
2) The MAX1385/MAX1386 then transmit the contents of the last register accessed starting with the most significant 8-bit byte of the 16-bit word. MSBs are sent first. Afterwards, the master needs to send an ACK bit. 3) The MAX1385/MAX1386 transmit the least significant 8-bit byte of the 16-bit word. MSBs are sent first. 4) The master issues a NACK bit and then generates a repeated START or STOP condition (Sr or P). Poll the current register by omitting step 4 and continuing to issue ACK bits after each data byte.
Figure 13 shows another useful sequence for a readmodify-write application.
Stringing Commands The MAX1385/MAX1386 allow commands to be strung together to minimize configuration time, which is especially useful in HS mode. Figure 12 shows an example of stringing a write and read command together to form a write/readback command.
Slave Address Byte The MAX1385/MAX1386 include a 7-bit-long slave address. The first 4 bits (MSBs) of the slave address are factory programmed and always 0x4h. The logic state of the address inputs (A2, A1, and A0) determine the 3 LSBs of the device address (see Figure 14). Connect A2, A1, and A0 to DVDD or DGND. A maximum of eight MAX1385/MAX1386 devices can be connected on the same bus at one time using these address inputs. The 8th bit of the address byte is a R/W bit. The address byte R/W bit is set to 0 to notify the device that a command byte will be written to the device next. The address byte R/W bit is set to 1 to notify the device that a control byte will not be sent and to immediately send data from the last accessed register.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 25. RDFLAG (Read)
BIT NAME X ADCBUSY ALUBUSY FIFOEMP FIFOOVER HIGHI2 LOWI2 HIGHT2 LOWT2 HIGHI1 LOWI1 HIGHT1 LOWT1 DATA BIT D15- D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POR X 0 1 0 0 0 0 0 0 0 0 0 0 Don't care 1 = ADC is busy 0 = ADC is not busy 1 = ALU is busy 0 = ALU is not busy 1 = FIFO is empty 0 = FIFO is not empty 1 = FIFO overflowed 0 = FIFO not overflowed 1 = Channel 2 high current threshold exceeded 0 = Channel 2 high current threshold not exceeded 1 = Channel 2 low current threshold surpassed 0 = Channel 2 low current threshold not surpassed 1 = Channel 2 high temperature threshold exceeded 0 = Channel 2 high temperature threshold not exceeded 1 = Channel 2 low temperature threshold surpassed 0 = Channel 2 low temperature threshold not surpassed 1 = Channel 1 high current threshold exceeded 0 = Channel 1 high current threshold not exceeded 1 = Channel 1 low current threshold surpassed 0 = Channel 1 low current threshold not surpassed 1 = Channel 1 high temperature threshold exceeded 0 = Channel 1 high temperature threshold not exceeded 1 = Channel 1 low temperature threshold surpassed 0 = Channel 1 low temperature threshold not surpassed FUNCTION
Command Byte The MAX1385/MAX1386 use read and write command bytes (see Figure 15). The command byte consists of 8 bits and contains the address of the register. The command byte also communicates to the device whether a read or write operation occurs. See the Register Description section for details on how to access specific registers through the command byte. Data Bytes Data bytes are clocked in/out of the device with the MSB first and the LSB last (see Figure 16). See the Register Description section for a description of data bytes for each register. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not active. The interface can support fast (400kHz) and high-speed (1.7MHz or 3.4MHz) data-transfer modes.
START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 17). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the interface transfer speed unchanged (see the Fast/High-Speed Modes section).
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
S OR Sr ADDRESS 7 BITS R/W 0 ACK WRITE COMMAND 8 BITS ACK DATA 8 BITS (MSB) ACK DATA 8 BITS (LSB) ACK
Sr
ADDRESS 7 BITS
R/W 1
ACK
DATA 8 BITS (MSB)
ACK
DATA 8 BITS (LSB)
NACK
Sr OR P
Figure 12. Write/Readback Sequence
S OR Sr
ADDRESS 7 BITS
R/W 0
ACK
READ COMMAND 8 BITS
ACK
Sr
ADDRESS 7 BITS
R/W 1
ACK
DATA 8 BITS (MSB)
ACK
DATA 8 BITS (LSB)
NACK
Sr
ADDRESS 7 BITS
R/W 0
ACK
WRITE COMMAND 8 BITS
ACK
DATA 8 BITS (MSB)
ACK
DATA 8 BITS (LSB)
ACK
Sr OR P
Figure 13. Read-Modify-Write Sequence
S SDA 0 1 0 0 A2 A1 A0 R/W ACK
SCL
1
2
3
4
5
6
7
8
9
Figure 14. Slave Address Byte
Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX1385/MAX1386 generate ACK bits. To generate an ACK, SDA must be pulled low before the rising edge of the ninth clock pulse and kept low during the high period of the ninth clock pulse (see Figure 20). To generate a NACK, SDA is pulled high before the rising edge of the ninth clock pulse and is left high for the duration of the ninth clock pulse.
Monitoring NACK bits allow for detection of unsuccessful data transfers. NACK bits can also be used by the master to interrupt the current data transfer to start another data transfer. The MAX1385/MAX1386 do not issue an ACK after the last byte of a full reset write to the Software Clear register.
Fast/High-Speed Modes At power-up, the bus timing is set for slow-/fast-speed mode (FS mode), which allows bus speeds up to 400kHz. The MAX1385/MAX1386 are configurable for
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
SDA C7 C6 C5 C4 C3 C2 C1 C0 ACK
SCL
1
2
3
4
5
6
7
8
9
Figure 15. Command Byte
SDA
D15
D14
D13
D12
D11
D10
D9
D8
ACK
D7
D6
D5
D4
D3
D2
D1
D0
NACK OR ACK
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 16. Data Bytes
S SDA
Sr
P
SCL
Figure 17. START and STOP Conditions
high-speed mode (HS mode), allowing bus speeds up to 3.4MHz. Execute the following procedure to change from FS mode to HS mode (see Figure 21). 1) Generate a START condition (S). 2) Send byte 00001XXX (X = don't care). The MAX1385/ MAX1386 issue a NACK bit. 3) HS mode is entered on the 10th rising clock edge. To remain in HS mode, use repeated START conditions (Sr) in place of the normal STOP conditions (P) (see Figure 22). All the same write and read formats supported in FS mode are supported in HS mode (with the replacement of repeated START conditions for STOP conditions). Generating a STOP condition (P) while in HS mode changes the bus speed back to FS mode.
SPI Digital Serial Interface
The MAX1385/MAX1386 feature a 4-wire SPI-compatible serial interface capable of supporting data rates up to 16MHz. Full data transfers occur in 24-bit sections. The first 8-bit byte is a command byte (C7-C0). The next 16 bits are data bits (D15-D0). Clock signal SCL may idle low or high but data is always clocked in on the rising edge of SCL (CPOL = CPHA).
Write Format Use the following sequence to write 16 bits of data to a MAX1385/MAX1386 register (see Figure 18): 1) Pull CSB low to select the device. 2) Send the appropriate write command byte (see the Command Byte section). The command byte is clocked in on the rising edge of SCL.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
A RISING EDGE OF CSB DURING THIS PERIOD COMPLETES A VALID WRITE COMMAND.
CSB SCL DIN CR/W C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 18. SPI Write Format
CSB SCL DIN DOUT CR/W C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 19. SPI Read Format
S
NOT ACKNOWLEDGE
SDA ACKNOWLEDGE SCL 1 2 8 9
Figure 20. Acknowledge Bits
3) Send 16 bits of data (D15-D0) starting with the most significant bit and ending with the least significant bit. Data is clocked in on the rising edges of SCL. 4) Pull CSB high.
Read Format Use the following sequence to read 16 bits of data from a MAX1385/MAX1386 register (see Figure 19): 1) Pull CSB low to select the device.
2) Send the appropriate read command byte (see the Command Byte section). The command byte is clocked in on the rising edges of SCL. 3) Receive 16 bits of data. Data is clocked out on the falling edges of SCL. 4) Pull CSB high.
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Command Byte The MAX1385/MAX1386 use read and write command bytes. The command byte consists of 8 bits and contains the address of the register (C7-C0, see Figures 18 and 19). The command byte also communicates to the device whether a read or write operation occurs. See the Register Description section for details on how to access specific registers through the command byte. Data Bytes Data bytes are clocked in/out of the device with the most significant bit first and the least significant bit last (D15-D0, see Figures 18 and 19). See the Register Description section for a description of data bytes for each register.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
HS-MODE MASTER CODE
S SDA
0
0
0
0
1
X
X
X
A
Sr
SCL FS MODE HS MODE
Figure 21. Changing to HS Mode
MASTER TO SLAVE SLAVE TO MASTER
FS MODE S MASTER CODE A Sr SLAVE ADDRESS R/W
FS MODE A COMMAND/DATA A P
FS MODE
N BYTES PLUS ACK Sr
HS MODE CONTINUES SLAVE ADD
HS MODE CAN ALSO BE CONTINUED WITH A COMMAND BYTE
Figure 22. Changing to FS Mode or Staying in HS Mode
Applications Information
ADC Clock Mode 11
See Figure 23 for an example of configuring a conversion scan for internal temperature, PGAOUT1, and ADCIN1 in clock mode 11 using the internal reference. Timing symbols are referenced in the Miscellaneous Timing Characteristics section. See Figure 24 for an example of configuring a conversion scan for ADCIN1, external temperature sensor 2, and PGAOUT2 in clock mode 11 using the internal reference. Timing symbols are referenced in the Miscellaneous Timing Characteristics section.
Leap-Frogging the DACs for 18 Bits of Resolution
Each DAC stage is configurable for leapfrog operation by using the 8-bit coarse DACs in conjunction with the 10-bit fine DAC. Use the following procedure for setting 18 bits of resolution: 1) Write to the Coarse DAC1/DAC2 Write-Through Low Wiper Input register (THRULO1/THRULO2) 2) Write to the Coarse DAC1/DAC2 Write-Through High Wiper Input register (THRUHIGH1/THRUHIGH2) with a value one higher or one lower than written to the low wiper register.
Temperature-Threshold Examples
Table 26 shows some examples of temperature settings in two's-complement form.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
tCNV11 tACQ11 tACQ11
CNVST
BUSY
TEMP SENSOR POWERS UP AND ACQUIRES IN ~6.7s
INTERNAL
INT REFERENCE POWERS UP IN ~60s
TEMP CONVERSION IN ~40s
IDLE, BUT REF AND TEMP SENSOR STAY POWERED UP
47s ACQUISITION FOR PGAOUT1 5.5s CONVERSION TIME FOR PGAOUT1
IDLE, BUT REF AND TEMP SENSOR STAY POWERED UP
2s ACQUISITION FOR ADCIN1 5.5s CONVERSION TIME FOR ADCIN1 5.5s CONVERSION TIME FOR ADCIN1
END OF SCAN, REF AND TEMP SENSOR POWER DOWN AUTOMATICALLY
USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER TO SET UP CONVERSION SCAN OF INTERNAL TEMPERATURE, PGAOUT1, AND ADCIN1
INTERNAL TEMPERATURE CONVERSION RESULT IS STORED IN FIFO
PGAOUT1 CONVERSION RESULT STORED IN FIFO
ADCIN1 CONVERSION RESULT STORED IN FIFO
Figure 23. ADC Clock Mode 11, Example 1
tCNV11 tAPUINT CNVST BUSY
5.5s CONVERSION TIME FOR ADCIN2
tACQ11
2s ACQUISITION OF ADCIN2
TEMP SENSOR POWERS UP AND ACQUIRES IN ~6.7s
2.0s ACQUISITION FOR ADCIN1
INTERNAL
INT REFERENCE POWERS UP IN ~60s
IDLE, BUT REF STAYS POWERED UP
TEMP CONVERSION IN ~40s
IDLE, BUT REF AND TEMP SENSOR STAY POWERED UP
END OF SCAN, REF AND TEMP SENSOR POWER DOWN AUTOMATICALLY
USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER TO SET UP CONVERSION SCAN OF ADCIN2, EXTERNAL TEMPERATURE SENSOR2, AND PGAOUT2
ADCIN2 CONVERSION RESULT STORED IN FIFO
EXTERNAL TEMPERATURE PGAOUT2 CONVERSION RESULT SENSOR 2 STORED IN FIFO CONVERSION RESULT STORED IN FIFO
Figure 24. ADC Clock Mode 11, Example 2
3) Write to the Fine DAC1/DAC2 Write-Through Input register without autocalibration (FINETHRU1/ FINETHRU2). If the coarse DAC1/DAC2 low wiper is higher than the coarse DAC1/DAC2 high wiper, invert the fine DAC1/DAC input register code.
The resulting output when the high wiper is higher than the low wiper is shown below: VDACREF 2
18
V x FINECODE + DACREF x LOWCODE 28
where FINECODE is the value written to the Fine DAC1/DAC2 Input register, and LOWCODE is the value
46 ______________________________________________________________________________________
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 27. Basic Software Initialization
COMMAND BYTE 0x64 0x64 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x60 0x74 0x76 0x7A 0x7C 0x52 0x56 DATA WORD 0x0008 0x0008 0x02A8 0x0EC0 0x02C1 0x0106 0x02A8 0x0EC0 0x02C1 0x0106 0x000F 0x0000 0x0000 0x00CC 0x0066 0x00CC 0x0066 0x01FF 0x01FF Bring the device out of shutdown mode. Set internal reference and both DAC channels on. Set the channel 1 high-temperature threshold to +85C. Set the channel 1 low-temperature threshold to -40C. Set the channel 1 high-current threshold to 4.3A for 50m RSENSE, AvPGA = 2, and VREFADC = 2.5V. Set the channel 1 low-current threshold to 1.6A for 50m RSENSE, AvPGA = 2, and VREFADC = 2.5V. Set the channel 2 high-temperature threshold to +85C. Set the channel 2 low-temperature threshold to -40C. Set the channel 2 high-current threshold to 4.3A for 50m RSENSE, AvPGA = 2, and VREFADC = 2.5V. Set the channel 2 low-current threshold to 1.6A for 50m RSENSE, AvPGA = 2, and VREFADC = 2.5V. Set AvPGA1 and AvPGA2 to 2, clock mode to 00 and ADC/DAC references to internal. Set ALARM, SAFE1, and SAFE2 to depend on nothing (POR). Set ALARM, SAFE1, and SAFE2 for push-pull/active-high (POR). Set coarse DAC1 high wiper to 204. Set coarse DAC1 low wiper to 102 (VGATE = 1.99V for MAX1385, VGATE = 3.98V for MAX1386). Set coarse DAC2 high wiper to 204. Set coarse DAC2 low wiper to 102 (VGATE = 1.99V for MAX1385, VGATE = 3.98V for MAX1386). Set fine DAC1 to midscale. Set fine DAC2 to midscale. DESCRIPTION
Table 26. Temperature-Threshold Settings Examples
TEMPERATURE SETTING -40C -1.625C 0C +27.125C +105C TWO'S COMPLEMENT 1110 1100 0000 1111 1111 0011 0000 0000 0000 0000 1101 1001 0011 0100 1000
Regulating VGS vs. Temperature
The MAX1385/MAX1386 can be used along with a microcontroller to perform closed-loop regulation of the LDMOS FET bias current. For example, software can read the temperature and use a calibrated look-up table to determine a new value for the gate drive. As an example, in noncontinuous conversion mode, read temperature from remote diode 1 by writing to the ADCCON register (0x62) with bit D1 set to 1. Wait for BUSY to go high and then low. Read the ADC result from the FIFO (0x80). The result bits D15-D12 = 0001 indicate the measurement source is the external temperature sensor DXP1/DXN1, and bits D11-D3 indicate two's-complement temperature in degrees Celsius. Bits D2, D1, and D0 are temperature subLSBs. Gate voltage drive range must be previously determined during initialization by setting the coarse DAC1 high and low limits. Write a new value to FINETHRU1 to immediately change the output GATE1 between the high and low wiper limits based on the previous temperature measurement. The regulation software may also use the alarm threshold limits to determine whether temperature and current
47
written to the Coarse DAC1/DAC2 Input Low Wiper register. The resulting output when the low wiper is higher than the high wiper is: V V - DACREF x FINECODE + DACREF x LOWCODE 18 2 28
Basic Software Initialization
The MAX1385/MAX1386 do not power on all internal blocks when full power is first applied. Software must write to register 0x64 twice with bit D7 set to 0 during initialization to enable full operation. A basic initialization sequence is shown in Table 27.
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Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 28. DAC Write Commands Without Autocalibration
ACTION REQUIRED Update fine DAC_ without triggering autocalibration. Update high wiper coarse DAC_ without triggering autocalibration. Update low wiper coarse DAC_ without triggering autocalibration. Immediately update fine DAC_ without triggering autocalibration. Immediately update high wiper coarse DAC_ without triggering autocalibration. Immediately update low wiper coarse DAC_ without triggering autocalibration. Update the high, low, and fine components of DAC_ simultaneously without triggering autocalibration. RECOMMENDED COMMAND SEQUENCE Write to FINE_. Write to LDAC to update fine DAC_. Write to HIWIPE_ with HCAL set to 0. Write to LDAC to update high wiper coarse DAC_. Write to LOWIPE_ with LCAL set to 0. Write to LDAC to update low wiper coarse DAC_. Write to FINETHRU_. Write to THRUHI_. Write to THRULO_. Write to HIWIPE_, LOWIPE, and FINE_. Write to LDAC to update DAC_. OTHER POSSIBLE COMMAND SEQUENCES Write to FINETHRU_ to immediately update fine DAC_. Write to THRUHI_ to immediately update high wiper coarse DAC_. Write to THRULO_ to immediately update low wiper coarse DAC_. None. None. None.
None.
VREFADC 1111 1111 1111 1111 1111 1110 BINARY OUTPUT CODE 1111 1111 1101 1111 1111 1100 VREFADC VREFADC 1 LSB = 4096 OUTPUT CODE FULL-SCALE TRANSITION
0111 1111 1111 0111 1111 1110 0111 1111 1101 0000 0000 0001 0000 0000 0000 1111 1111 1111 1 LSB = +0.125C
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0 1 2 3 4093 INPUT VOLTAGE (LSB) 4095 1000 0000 0010 1000 0000 0001 1000 0000 0000 -256C 0C TEMPERATURE (C) +255.875C
Figure 25. ADC Transfer Function
Figure 26. Temperature Transfer Function
limits are within the safe operating area. Configure the ADC for continuous conversions to allow continuous measurement and testing against configured alarm thresholds. Connect SAFE_ to OPSAFE_ to immediately force the gate drive to GATEGND in the event of an alarm-related condition (current or temperature).
Triggering DAC Calibration
Performing the autocalibration routines requires use of the internal ADC, the internal ALU, and can also increase the power dissipation of the part. Tables 28 and 29 detail which commands trigger autocalibration and which commands do not.
48
______________________________________________________________________________________
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Table 29. DAC Write Commands with Autocalibration
ACTION REQUIRED Update fine DAC_ and trigger autocalibration. RECOMMENDED COMMAND SEQUENCE Write to FINECAL_. Autocalibration begins after writing to FINECAL_. Write to LDAC to update fine DAC_. Write to HIWIPE_ with HCAL set to 1. Autocalibration begins after writing to LDAC and high wiper coarse DAC_ is updated thereafter. Write to LOWIPE_ with LCAL set to 1. Autocalibration begins after writing to LDAC and low wiper coarse DAC_ is updated thereafter. Write to FINECALTHRU_. This action is not possible. See the recommended sequence above "Update high wiper coarse DAC_ and trigger autocalibration." This action is not possible. See the recommended sequence "Update low wiper coarse DAC_ and trigger autocalibration." Write to HIWIPE_ with HCAL set to 1. Write LOWIPE_ with LCAL set to 1. Write to LDAC to update high and low wipers with autocalibrated values. Write to FINECALTHRU_ to trigger fine DAC_ autocalibration and update DAC_. OTHER POSSIBLE COMMAND SEQUENCES Write to FINECALTHRU_ to immediately update fine DAC_.
Update high wiper coarse DAC_ and trigger autocalibration.
None.
Update low wiper coarse DAC_ and trigger autocalibration. Immediately update fine DAC_ and trigger autocalibration. Immediately update high wiper coarse DAC_ and trigger autocalibration.
None.
None.
None.
Immediately update low wiper coarse DAC_ and trigger autocalibration.
None.
Update the high, low, and fine components of DAC_.
HIWIPE_ and LOWIPE_ can be written to in any order but must be followed by LDAC and then a fine DAC_ write (to FINECALTHRU_ or FINECAL_ with another LDAC). This ensures that the fine DAC_ autocalibration is run after the coarse DAC_ autocalibration.
______________________________________________________________________________________
49
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Typical Operating Circuit (I2C Mode)
5V 5V
EXTERNAL REFERENCE SCL SDA DVDD SCL SDA/DIN ALARM MICROCONTROLLER BUSY SAFE2 SAFE1 +5V GATE1 A0/CSB A1/DOUT A2/N.C. SEL OPSAFE1 OPSAFE2 CNVST (AT LDMOSFET) DXP1 CS2+ DXN1 (AT LDMOSFET) 5V DXP2 CS2CF* RF* ADCIN1 ADCIN2 CS1GATEVDD AVDD REFDAC REFADC
DRAIN SUPPLY
CS1+ C F* RF*
MAX1385 MAX1386
DGND RF OUTPUT RF INPUT
DRAIN SUPPLY
DXN2 PGAOUT1 PGAOUT2 AGND
GATE2 GATEGND RF OUTPUT RF INPUT
*SELECT RF AND CF BASED ON DESIRED FILTER CUT-OFF FREQUENCY. LIMIT RF TO MINIMIZE OFFSET ERRORS.
50
______________________________________________________________________________________
Dual RF LDMOS Bias Controllers with I2C/SPI Interface
Pin Configuration
OPSAFE1 CS1+ CS1TOP VIEW N.C. N.C. N.C. CS2+ OPSAFE2 N.C. GATE1 GATE2 CS2-
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 48 TQFN-EP PACKAGE CODE T4877-6 DOCUMENT NO. 21-0044
MAX1385/MAX1386
36 35 34 33 32 31 30 29 28 27 26 25
N.C. N.C. N.C. PGAOUT1 A2/N.C. N.C. SCL SDA/DIN A1/DOUT N.C. BUSY DVDD
37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19 18 17 16 15 14
GATEVDD GATEGND AGND AGND AGND N.C. AVDD PGAOUT2 ADCIN2 ADCIN1 DXN2 DXP2
MAX1385 MAX1386
*EXPOSED PAD
1 2 3 4 5 6 7 8 9 10 11 12
13
+
REFDAC REFADC DXP1
A0/CSB
DGND SAFE1
CNVST SEL ALARM
SAFE2 N.C.
TQFN
*EXPOSED PAD INTERNALLY CONNECTED TO AGND
______________________________________________________________________________________
DXN1
51
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386
Appendix: Recommended Power-Up Code Sequence
The following section shows the recommended startup code for the MAX1385. This code ensures clean startup
REGISTER MNEMONIC SHUT SHUT SCLR SCLR SCLR SCLR SHUT SHUT DCFIG PGACAL REGISTER ADDRESS (hex) 0x64 0x64 0x68 0x68 0x68 0x68 0x64 0x64 0x30 0x4E CODE WRITTEN 0x0080 0x0080 0x0100 0x0200 0x0100 0x0200 0x0080 0x0080 0x000A 0x0002 Removes the global power. Powers up all parts of the MAX1385 and forces the internal reference to remain powered. The internal oscillator is required for the subsequent reset command. Arms the full reset. Completes the full reset. Arms the full reset.* Completes the full reset.* Removes the global power. Powers up all parts of the MAX1385 and forces the internal reference to remain powered. The internal oscillator is required for the subsequent reset command. Selects internal references for both DAC and ADC. Runs autocalibration on both PGA channels to set the input referred offset to < 50V. Busy goes low after approximately 30ms and then the VGATE DACs can be set.
of the part, irrespective of power-supply ramp speed and starts the device regulating to 312.5mV on both channels. Change the THRUDAC writes to change the voltage across the sense resistor. Note it should be run after the power supplies have stabilized.
NOTES
*Double reset. This ensures that the internal ROM is reset correctly after power-up and that the ROM data is latched correctly irrespective of power-supply ramp speed.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
52 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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